Are Models Always The Answer?

Given the shift to system level design and the need to make tradeoffs early in the design process, much emphasis is placed on modeling, and for good reason.

Tobias Bjerregaard, CEO of Teklatech reminded that power integrity analysis and signal integrity analysis evolved to be more or less a checkmark from many companies. “They run it and then say, ‘OK, it is fine,’ but they don’t think about whether it correlates with the actual chips. Some companies do and some company spend years to make sure it does.”

In fact, he said it is surprising how many companies run the signoff analysis wrong and don’t even realize it. “It’s very very troubling because they say, ‘We optimized with your tool and the signoff tells us there’s nothing happening.’ We know something is happening so we look at the signoff set up and often we discover they are not running with propagated clock timing they are running with ideal clocks, so of course you can’t see the difference. The problem there is that when you do signoff you should see the design as it is not with a lot of early-stage assumptions.”

Further, power integrity analysis is moving is moving backwards toward earlier design stages, he continued. “Once people have a hold on the signoff analysis, they analyze and they see what it’s going to be like and then they tape out. Then they start saying, ‘We want to fix this. We don’t just want to know what’s up and what’s down — we want to do something about it.’ Then they have to loop quite far back maybe for placement, or to reroute the power grid or they want to resynthesize the design. Those are long loops.”

This has driven earlier analysis but the main problem with that is coherency in the flow. “How can you correlate early with late analysis? One of the problems there is the models that are being used – power models of the individual cells for the signoff tools are proprietary and they don’t always match what you find in a .lib file,” Bjerregaard said. “That’s a huge problem because you have the step where you move your analysis anywhere in the flow: whether it is at RTL or gate level netlist level, and then when you go to signoff you have completely different models. You can use it but it’s difficult to really optimize early stage because if you don’t have the same view you can’t converge toward the same result. Moving forward we will have more focus on accurate early-stage models and standardization and we have great hopes for CCS [composite current source] which provides accurate dynamic current waveforms in liberty that can be used and signoff as well.”

But, cautions Drew Wingard, CTO of Sonics, you have to be careful not to end up in that loop where you make a change to the architecture and therefore none of the models are accurate anymore.

“You’ve got to break out of that loop where, ‘I can’t make the choice because I don’t have the data, and I I can’t get the data until I make the choice,’” he asserted.

The way to break out of that loop is to go back to some first principles and work with some rules of thumb. “I can say I know this is about this many gates and all I’m trying to run at this frequency so I can be a bit conservative in my modeling about what a worst case pattern would look like here. There are ways of doing that kind of modeling but to get from that conservative guess to a, ‘How is that going to energize my power network model and therefore how much noise am I going to get on my supply? Oh, by the way I have to make some assumptions about how many pins there are going to be, and what kind of package it’s going to go on, and what kind of substrate that thing is going to be mounted on,’ now I can actually build a power network model. That is so far down the path from when these decisions are being made so I don’t think it’s the power model of the components that is the bigger problem here I think it is actually trying to feed forward the information about any model for that component pushed through the rest of the back end and the power network and the package.”