Arvind Vel

  (all posts)
Arvind Vel is director of application engineering at ANSYS.

Author's Latest Posts

7nm Design Success Starts With Multi-Domain Multi-Physics Analysis
By Arvind Vel - 28 Nov, 2016 - Comments: 1

Companies can benefit from advancements in the latest semiconductor process technology by delivering smaller, faster and lower power products, especially for those servicing mobile, high performance computing and automotive ADAS applications. By using 7nm processes, design teams are able to add a lot more functionality onto a single chip and lower the power consumption by scaling operating volt... » read more

FinFET Reliability Issues
By Arvind Vel - 13 Mar, 2014 - Comments: 0

The 16nm FinFET node has introduced several new challenges in the IC design community. In addition to the complexity of power-noise and electromigration (EM) verification, thermal reliability has become a major concern for both chip and package designers. With the three-dimensional architecture of FinFET devices, new simulation approaches are being used to model thermal behavior of the die in o... » read more

How Reliable Are Interconnects In 16nm FinFET Designs?
By Arvind Vel - 05 Dec, 2013 - Comments: 0

The 16nm FinFET process node is rapidly becoming the preferred choice for advanced Integrated Circuit (IC) designs. The 16nm node’s lower standby leakage characteristics and increased drive strength capability enable IC designers to push the boundaries of low power – high performance designs. However, the choice of the node is also accompanied by reduced reliability margins, requiring desig... » read more

Reliability Challenges In 16nm FinFET Design
By Arvind Vel - 10 Oct, 2013 - Comments: 1

As the IC industry rapidly adopts the 16nm technology node, IC designers are faced with a new wave of reliability challenges. The 16nm node has introduced several changes in the way that the devices are fabricated and how the metal stack-up is built. On one hand designers gain speed, leakage and density improvements. On the other, reliability engineers need to address the narrowing electromigra... » read more

Design For Reliability
By Arvind Vel - 11 Oct, 2012 - Comments: 0

By Arvind Shanmugavel Faster processors, lowered power targets and shrinking technology have increased the complexity of integrated circuit (IC) reliability analysis. With the 20nm node becoming mainstream, IC design teams are fast re-tooling their analysis methodologies to simulate and capture various reliability failure mechanisms. Electromigration (EM) analysis, thermal analysis and Electro... » read more

New Reliability Issues
By Arvind Vel - 14 Jun, 2012 - Comments: 0

By Arvind Shanmugavel Reliability of ICs is a topic of growing concern with every technology node migration. With the onset of the 20nm process node from different foundries, reliability verification has taken center stage in design kits—and for good reason. Reliability margins have continued to decrease and have reached an inflection point at the 20nm node. The design and EDA communities ha... » read more

Reliability Verification For Smart ICs
By Arvind Vel - 05 Apr, 2012 - Comments: 0

By Arvind Shanmugavel The electronic brains behind today’s advanced systems are smart ICs, paving the way for consumer electronics, energy, biomedical, automotive and avionics industries. Power efficiency and system integration are keys to the success of these smart systems. The IC industry has swiftly responded with state-of-the-art low-power techniques and chip integration initiatives f... » read more

Noise Coupling Analysis
By Arvind Vel - 06 Oct, 2011 - Comments: 0

By Arvind Shanmugaval Integrating digital and mixed-signal IP blocks in SoCs poses a considerable challenge to verification of power/ground and substrate noise. Traditional methods of power supply noise analysis are unable to meet the demands of today’s highly integrated designs with multiple low- power design techniques. Existing methods also do not provide sufficient capacity or the capabi... » read more

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