Noise Coupling Analysis

Crossing the line from nice-to-have to must-have; modeling the source of noise, picking a medium and determining the victim.


By Arvind Shanmugaval
Integrating digital and mixed-signal IP blocks in SoCs poses a considerable challenge to verification of power/ground and substrate noise. Traditional methods of power supply noise analysis are unable to meet the demands of today’s highly integrated designs with multiple low- power design techniques. Existing methods also do not provide sufficient capacity or the capability for predicting the impact of transient power supply noise on key circuit parameters.

Predicting noise coupling in circuits will typically need accurate modeling of the source of noise, the medium of propagation, and the impact on the victim. The source of noise is usually the injection of current into the power/ground network or the substrate network. The medium of propagation is commonly the power/ground mesh or the substrate model. And finally, the victim is usually the circuit that is impacted by the noise.

Failure of Traditional Approaches
Power/ground noise is usually transient in nature. Without modeling the transient behavior of noise, it is impossible to predict its impact on the victim circuits. Traditionally, power/ground noise is modeled as a static behavior in the form of IR drop. However, to model the temporal and spatial activity of noise you need to perform a dynamic or transient simulation. Due to the capacity limitation of SPICE simulators, designers use simplified SPICE netlists to analyze and validate the impact of power ground noise on ICs. These approaches cannot comprehend the full-chip scale and nature of the substrate noise injection and propagation. Also with new process technologies, assuming that past techniques are applicable to future designs can result in over-design or require several chip revisions to meet the specification.

The Need for Power Noise Verification
The shift in the semiconductor industry to become more mobile centric has prompted several changes in design paradigms. The first and foremost being the move to low-power design styles. Low-power designs typically have multiple power islands at different voltages for better power savings. With multiple power islands, the verification complexity of transient noise is critical, especially through the substrate. Standby power saving techniques such as power-gating also impacts the verification complexity of power noise due to in-rush current. The turning on and turning off of various power gated domains needs to be modeled with the complete impact of the package along with the die. The low ambient and high transient current modeling must be accurately captured during the noise verification analysis.

Integrated Platform for Analog/Mixed-Signal, Custom Design Verification and Analysis
A simulation-based approach with large capacity and smart modeling technology is needed for verifying power supply noise on highly integrated SoCs. An SoC-level power/ground/substrate noise analysis and verification platform is needed to address static and dynamic power integrity requirements for today’s IP and SoCs. The SoC/IP validation methodology should verify power grid connection problems, identify high voltage drop causing mechanisms, identify noise coupling scenarios between gated and un-gated power domains, and also isolate EM bottlenecks. It must also provide the ability to model the complete substrate network to see the full impact of noise on victim circuits. IP model roll-up for capturing various transient states is also important in the verification platform. These models should also have the ability to integrate into the SoC to perform system-level simulations for the complete behavior of noise at the transistor-level. The industry needs a comprehensive solution with the capability to provide full-chip capacity and Spice-level accuracy for transient power-ground noise and EM analysis. It needs a solution with a built-in extraction and simulation engine for fast incremental validation, and model generation capabilities for hierarchical full-chip and system-level analysis, along with a single-kernel flow to help analyze and predict coupling of power-ground and substrate noise in a design.

–Arvind Shanmugavel is director of applications engineering at Apache Design.