FinFET Reliability Issues

Thermal density increases by 25% compared with planar devices, raising questions about EM and longevity.


The 16nm FinFET node has introduced several new challenges in the IC design community. In addition to the complexity of power-noise and electromigration (EM) verification, thermal reliability has become a major concern for both chip and package designers. With the three-dimensional architecture of FinFET devices, new simulation approaches are being used to model thermal behavior of the die in order to see localized temperature variations. Chip designs in the FinFET nodes are beginning to include thermal analysis as a routine sign-off metrics.

Thermal Modeling for FinFETs
In addition to the width and length, the CMOS FinFET device adds a third dimension to the size, namely the fin height. The fin height provides the advantage of better electrostatic control of the channel, yielding an increased switching current. Typically, FinFET devices see a 25% increase in their current density when compared to the previous generation planar devices. This increase in current density coupled with the new three-dimensional geometry has exacerbated the heat dissipation problem for FinFETs.

Thermal characteristics for the 16nm FinFET node are much more complex to model due to the fin dimension of the device. For the planar CMOS process, the heat generated is usually dissipated through the silicon substrate and the device has a low vertical thermal coupling to the metal above. In contrast, the FinFET process device has a higher vertical thermal coupling to the metal interconnects above due to the heat trapped in the fins. The higher vertical thermal coupling is mainly due to the restricted heat escape pathways of the device fin and the increased thermal resistance of the silicon substrate.

Research also has shown that the temperature increase on the fins and neighboring metal interconnects is strongly dependent on the height of the fin. Therefore, the foundries are carefully selecting the optimal fin height to ensure thermal reliability. In addition, the substrate thickness for the FinFET devices has to be reduced significantly to provide more efficient heat sink.

Simulating the complete thermal behavior of an IC requires modeling the heat generated and dissipated on the IC along with the package thermal characteristics. Because modeling of the dissipated heat for FinFET devices is much more complex, foundries have developed empirical equations representing the substrate temperature increase based on device density, activity factor and operation frequency. These empirical equations, along with the self-heating calculation of the metal interconnects, can provide a very accurate estimate of the local temperature increases on the die. By adding package thermal characteristics, one can compute the converged temperature on the die for every metal layer at a micron resolution. This on-die thermal profile can vary drastically from one location to another and for different metal layers. The large temperature variation is an important factor to consider for interconnects reliability analyses such as electromigration checks.


Impact on Electromigration and Lifetime
The Mean Time to Failures (MTTF) for metal interconnects on an IC has an inverse exponential dependence on temperature. A small increase in temperature can lead to a large decrease in the MTTF for a device. Higher current densities, lower EM limits and larger temperature variations on FinFET designs have caused the perfect storm for reliability verification engineers. EM no longer can be signed off using aggressive margins or a ‘correct-by-construction’ approach. A comprehensive thermal-aware EM signoff methodology needs to be adopted for FinFET designs.

A typical IC can have several regions of high and low activity. The regions with high activity typically will see a larger increase in temperature due to Joules self-heat. Historically, IC designers sign off EM using the worst case temperature. With the FinFET node, using a worst-case temperature can cause many false EM violations in areas of lower temperature. With the reduced EM margins and higher thermal sensitivities in the 16nm node, IC designers are increasingly using more realistic temperature-aware EM sign off.


Thermal characteristics in the 16nm FinFET process are typically worse due to tightly packed fins and poor heat escape pathways. Using the worst-case temperature could lead to pessimistic EM results due to the exponential dependence of temperature on EM limits. Thermal-aware EM analysis designer can reclaim the margins lost due to worst-case temperature usage. Using accurate spatial thermal distribution of the die for EM analysis can significantly decrease the number of false EM violations during sign-off.

With increased interconnect resistances and high switching device currents, self-heat checks for signal nets are major sources of concern. Self-heat EM checks, including the RMS signal EM analysis, are mandatory for sign-off at the SoC level in the 16nm node.


System-Level Thermal Modeling
ICs eventually will be part of a platform or a system. Being able to model the source of heat with spatial accuracy in a system can greatly reduce the prototyping stage of the product. Today’s mobile products are mostly passive cooled with IC components in very close proximity to each other. System-level thermal tools need to model information such as air flow in addition to chip thermal characteristics. Computational Fluid Dynamic (CFD) simulation platforms are typically used to model such behavior.

Thermal reliability analysis has become an integral part of the IC design ecosystem. With the FinFET technology node now being mainstream, empirical models from foundries are being combined with IC-package thermal analysis to obtain thermal profiles with a micron resolution. Reliability verification is seeing a paradigm shift to thermal-aware analysis and signoff. Package thermal models with spatial accuracy bring a new level of accuracy for simulating passively cooled electrical subsystems.

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