tag: sign off

Signoff Of Synthesis-Optimized Registers
By Ed Sperling - 17 Jun, 2026 - Comments: 0

How do you know when you sign off on a complex chip design that everything is going to work? There are more variables, more elements that need to be verified, and more waivers that need to be generated. Suresh Barla, senior director of field applications at Synopsys, talks about how to ensure that RTL is fully optimized for PPA targets in large designs that can include hundreds of millions of g... » read more

Current Problems Grow For Power Delivery
By Brian Bailey - 16 Oct, 2025 - Comments: 0

IR drop is becoming more problematic for a growing proportion of designs, an indication that the power delivery network (PDN) is not providing enough current to parts of the design when required. Unfortunately, there is no easy fix to this problem. In the past, when voltages were much higher, a small voltage droop didn't really matter. At the same time, wires were much thicker and presented ... » read more

Using AI/ML To Minimize IR Drop
By Ann Mutschler - 11 Apr, 2024 - Comments: 1

IR drop is becoming a much bigger problem as technology nodes scale and more components are packed into advanced packages. This is partly a result of physics, but it's also the result of how the design flow is structured. In most cases, AI/ML can help. The underlying problem is that moving to advanced process nodes, and now 3D-ICs, is driving current densities higher, while the power envelop... » read more

Next-Gen Power Integrity Challenges
By Ed Sperling - 14 Dec, 2023 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss power integrity challenges and best practices in designs at 7nm and below, and in 2.5D and 3D-IC packages, with Chip Stratakos, partner, physical design at Microsoft; Mohit Jain, principal engineer at Qualcomm; Thomas Quan, director at TSMC; and Murat Becer, vice president at Ansys. What follows are excerpts of that conversatio... » read more

Shift Left, Extend Right, Stretch Sideways
By Brian Bailey - 27 Jul, 2023 - Comments: 0

The EDA industry has been talking about shift left for a few years, but development flows are now being stretched in two additional ways, extending right to include silicon lifecycle management, and sideways to include safety and security. In addition, safety and security join verification and power as being vertical concerns, and we are increasingly seeing interlinking within those concerns. ... » read more

Improving Verification Predictability And Efficiency Using Big Data
By Siemens EDA - 08 Feb, 2023 - Comments: 0

Big data is a term that has been around for decades. It was initially defined as data sets captured, managed, and processed in a tolerable amount of time beyond the ability of normal software tools. The only constant in big data’s size over this time is that it’s been a moving target driven by improvements in parallel processing power and cheaper storage capacity. Today most of the industry... » read more

Automated Late Stage Timing-Aware Dynamic Voltage Drop ECO
By Manoj Chacko - 09 Jan, 2023 - Comments: 0

One of the never-ending frustrations for electrical engineers is having to deal with counterproductive real-world effects that they wish would just go away. Examples include switch bounce, metastability, and contact resistance. For IC designers, dynamic voltage drop (DVD), also known as IR drop, is one of those unfortunate facts of the profession. There’s no way to avoid it; every trace and w... » read more

Why Comparing Processors Is So Difficult
By Brian Bailey - 10 Mar, 2022 - Comments: 2

Every new processor claims to be the fastest, the cheapest, or the most power frugal, but how those claims are measured and the supporting information can range from very useful to irrelevant. The chip industry is struggling far more than in the past to provide informative metrics. Twenty years ago, it was relatively easy to measure processor performance. It was a combination of the rate at ... » read more

Setting Ground Rules For 3D-IC Designs
By Ed Sperling - 12 Jan, 2022 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss the changes in design tools and methodologies needed for 3D-ICs, with Sooyong Kim, director and product specialist for 3D-IC at Ansys; Kenneth Larsen, product marketing director at Synopsys; Tony Mastroianni, advanced packaging solutions director at Siemens EDA; and Vinay Patwardhan, product management group director at Cadence... » read more

Challenges With Stacking Memory On Logic
By Ed Sperling - 22 Dec, 2021 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss the changes in design tools and methodologies needed for 3D-ICs, with Sooyong Kim, director and product specialist for 3D-IC at Ansys; Kenneth Larsen, product marketing director at Synopsys; Tony Mastroianni, advanced packaging solutions director at Siemens EDA; and Vinay Patwardhan, product management group director at Cadence... » read more

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