Automated Late Stage Timing-Aware Dynamic Voltage Drop ECO

One of the never-ending frustrations for electrical engineers is having to deal with counterproductive real-world effects that they wish would just go away. Examples include switch bounce, metastability, and contact resistance. For IC designers, dynamic voltage drop (DVD), also known as IR drop, is one of those unfortunate facts of the profession. There’s no way to avoid it; every trace and wire has resistance, and voltage drops as current travels through it.

DVD creates significant challenges, especially at lower process nodes such as 5/3-nm, where the metal pitch has high resistance and therefore higher DVD. Increased chip operation frequency and power consumption also raise DVD, which causes changes in cell delays. This impacts setup and hold timing and may reduce the performance of the design. Excessive DVD can also reduce the operational life cycle of the silicon. It is therefore critical to tape out the chip with as little DVD as possible.

Traditionally, DVD analysis has been performed late in the development process, after the chip design has been placed and routed. Only at that stage can accurate resistance and capacitance (RC) values be extracted from the layout. If the analysis looks clean, then there is no problem, but this never happens. The designer always discovers excessive DVD that must be fixed before the chip is taped out.

DVD issues can be addressed by using an engineering change order (ECO) tool that calculates adjustments to the layout and sends a change list back to the place and route tool. After the layout has been updated, DVD analysis is re-run to see if the problems have actually been fixed. If the second DVD run is clean, the design can be signed off, but this almost never happens. It usually takes multiple iterations through the analysis-ECO-layout loop before the results are acceptable and DVD signoff can be achieved.

Iterating at this late stage of the chip project is expensive, consuming precious time and resources. The turnaround time (TAT) for each loop is significant, and many of the fixes are heuristic and manual. It is expensive in both runtime and engineering time for designers to analyze root causes of DVD problems and give guidance to the ECO tool. Some types of solutions for DVD problems, such as strengthening the power grid, are not possible when ECO is performed at such a late stage in the project timeline.

In addition, static timing analysis (STA) also needs to be performed on each changed layout and signing off DVD and timing simultaneously in two different tools is very difficult. DVD fixes suggested by the ECO tool may “break” design timing, requiring even more iterations to resolve. It is common for the DVD signoff process to take weeks or even months to complete.

What’s needed is an automated late-stage timing-aware DVD ECO solution with several requirements:

• The ECO tool must be tightly integrated with the golden DVD analysis tool
• The ECO tool must be tightly integrated with the golden STA tool
• Timing and DVD must be optimized together
• The TAT for each DVD iteration must be as short as possible
• The number of late-stage DVD iterations must make minimal impact to the design cycle time and be reduced to one or a few

Therefore, a live connection with instantaneous feedback between ECO and DVD analysis is the key to meeting these requirements. This allows the ECO tool to send proposed layout changes for DVD analysis on the fly rather than as a separate step. The ECO tool knows instantly whether each proposed change improves DVD and can make adjustments as needed, essentially moving the manual iterations in the traditional flow into a single automated run.

A proven solution is available today. Synopsys PrimeClosure and Ansys RedHawk-SC have been tightly connected into a holistic flow that meets all the requirements above. Synopsys PrimeClosure golden signoff ECO is architected to handle very high-capacity designs and integrated with Synopsys PrimeTime, the industry’s golden STA signoff tool. Ansys RedHawk-SC is the gold standard for DVD analysis, able to capture and measure the causes of DVD and pass targeted information to Synopsys PrimeClosure.

The live connection between these two tools enables instant evaluation of proposed ECO changes. The on-the-fly analysis can identify the root causes of DVD issues and guide the ECO process in making the right changes to resolve these issues without impacting timing. This is the industry’s first solution for automated late-stage timing-aware DVD ECO to overcome the limitations of the traditional iterative flow.

The value of this solution has been demonstrated in numerous case studies of real-world chip designs. The results from a 4-nm design were presented at the 2022 SAFE (Samsung Advanced Foundry Ecosystem) Forum and the 2022 Design Automation Conference (DAC). The automated flow reduced the number of DVD violations by 79% and improved the worst-case DVD by 16%. On a 6-nm design, the ECO count was reduced by 40% and the worst drop was improved by more than 21%.

In addition to improving silicon reliability and performance, effective DVD ECO can reduce operating voltage and thereby save peak and average power. Another case study showed that supply voltage was reduced by 1% on a production chip at tapeout as the result of the Synopsys-Ansys flow.

There is no doubt that automated late-stage timing-aware DVD ECO is essential for modern chip designs. It replaces the traditional iterative, labor-intensive approach and hits design targets in a fraction of the time. Find out more here.