Redefining Progress

After lots of wrangling over the whether Moore's Law is alive, dead, or languishing at somewhere in between, that discussion now seems about as relevant as the look and feel of Apple's early Macintosh operating system—an issue that back in the 1980s spawned a very public war with Microsoft. Today that argument is about as relevant as whether Betamax was better than VHS. Whether it's Moor... » read more

The Route To Faster Physical Verification And Better Designs

By Nancy Nguyen & Jean-Marie Brunet As we’ve moved to today’s leading-edge nodes, physical layout designers have faced more and more challenges to get their design to tape-out on schedule. Timing becomes increasingly difficult to converge, power reduction for both IR and leakage becomes a big issue, and most importantly, how do we meet all of the ever-growing and more complex signoff d... » read more

Changing The Meaning Of Sign-Off

Chip development teams are faced with an ever-increasing number of power integrity and reliability challenges these days, especially as designs adopt FinFET technology. Even those with the most thorough sign-off checks often encounter unexpected surprises that quickly turn into tape-out hurdles, or worse yet, extensive re-design. The best way to avoid this scenario and ensure a smoother sign-of... » read more

System-Aware SoC Power, Noise And Reliability Sign-Off

In globally competitive markets for mobile, consumer and automotive electronic systems, the critical success factors are power consumption, performance and reliability. To manage these conflicting requirements, design teams consider multiple options, including the use of advanced process technology nodes — especially FinFET-based devices. These advanced technology nodes allow chips to operate... » read more

FinFET Reliability Issues

The 16nm FinFET node has introduced several new challenges in the IC design community. In addition to the complexity of power-noise and electromigration (EM) verification, thermal reliability has become a major concern for both chip and package designers. With the three-dimensional architecture of FinFET devices, new simulation approaches are being used to model thermal behavior of the die in o... » read more

How To Achieve 10X Faster Power Integrity Analysis And Signoff

In our mobile computing era, system-on-chip (SoC) design has become much more complex, with challenges from complex design rules on advanced process nodes, low-power circuitry design techniques, and increasing circuit sizes. Power integrity is a crucial part of successful design signoff. This paper discusses a new tool that speeds power integrity analysis and signoff by 10X compared to other te... » read more

Roundtable: Is The Chip Ready

Mobile devices demand complex chips—so complex to build that signoff has become something of a balancing act between what the verification teams believe is good enough and time-to market demands. Low-Power/High-Performance Engineering talked about this with Simbal Rafiq, director of engineering at Applied Micro; Robert Hoogenstryd, senior director of marketing for design analysis and signoff ... » read more

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