Why netlist clock domain crossing is now an essential complement to RTL CDC at advanced nodes and in AI chips.
Tanveer Singh, senior staff consulting applications engineer at Synopsys, explains why netlist clock domain crossing is now an essential complement to RTL CDC, why CDC issues are worse at advanced nodes and in AI chips, and why dealing with CDC effectively is becoming a competitive requirement for performance and low power.
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Tanveer listed 4 examples of potential issues why netlist CDC is needed: clock network, sequential optimization in synthesis, clock gating, and AND-OR for mux. To me, only last one is a valid reason, which is caused by bad design. If you are a good designer, you would never allow tool to synthesize the clock mux, and would manually instantiate the clock mux cell from library as there are always dedicated (specially designed) clock mux cells available. But, I agree that not every designer pays attention to it.
My point is that the reasons listed are not very convincing for moving to netlist CDC. The example listed is the clock mux.
To support netlist CDC, speed and capacity are the key. If you cannot support full-chip run, the value is significantly diminished.
DFT logic also can introduce new CDC paths ..these can be verified only by Netlist CDC