Addressing Thermal Reliability In Next-Gen FinFET Designs

How to reduce the effects of heat while minimizing design time.


The next generation of chips on the 10/7nm finFET processes will be able to cram more devices into same area while also boosting performance, but there’s a price to pay for that.

The 3D fin structures trap heat, so the the temperature rises on the device and there is no way to dissipate that heat. This combination of higher current density, higher performance and higher temperature has a detrimental effect on the lifetime of devices. This is particularly bad in safety-critical markets, such as automotive, where there are very stringent rules for safety and reliability.

In that market and many others, design for reliability no longer can be an afterthought.

Thermal effects are particularly problematic at advanced nodes because EM limits are already lower than at previous nodes. Fixing or waiving EM violations becomes more complex, more tedious, and can delay time to market.

From a process reliability perspective, EM degradation is inherently statistical and can be represented as lognormal equation. Also, at the SoC level, an individual interconnect’s EM becomes arbitrary, especially with a large amount of on-die interconnect segments. That makes statistical EM budgeting (SEB) essential for reliability analysis because it allows design teams to prioritize design fixes.

A statistical EM model or budget (SEB) is developed, and a failure-in-time (FIT) analysis (based on logarithmic Black’s equation) is performed to determine if a chip/block/IP meets the budget. From Black’s equation we can see that mean time to failure is exponential to the temperature. The adverse self-heating problems with finFETs and lack of heat sinks for dissipation increases the on-chip temperature, which directly impacts the chip’s lifetime. Hence, a temperature-aware FIT analysis is now a requirement for advanced technology nodes. Typically, a FIT budget based on statistical model is determined for the entire chip, although it can be apportioned into sub-blocks, as well. When a thermally aware FIT analysis is performed, and if it passes the budget with EM violations, those EM violations are waived off! On the other hand, if a chip/block violates the FIT budget but passes the EM check, designers still have to fix EM to meet the budget. That makes a thermally aware SEB a handy way to achieve EM sign-off without over-design.

ANSYS’ Totem and RedHawk solutions provide the capability to perform thermally aware reliability analysis along with FIT analysis. Also, ANSYS’ Chip Package System (CPS) thermal solutions offer comprehensive chip level thermal and chip-aware system-level thermal analysis to achieve thermal integrity and power-thermal convergence across the spectrum of chip, package and board. View the webinar on “Thermal, EM and ESD Reliability Signoff for Next-Generation FinFET Designs” to learn about the increasing need for reliability and how to leverage ANSYS’ product portfolio to sign off on next-generation electronics systems designed for automotive, mobile and high-performance applications.

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