Addressing Thermal Reliability In Next-Gen FinFET Designs


The next generation of chips on the 10/7nm finFET processes will be able to cram more devices into same area while also boosting performance, but there's a price to pay for that. The 3D fin structures trap heat, so the the temperature rises on the device and there is no way to dissipate that heat. This combination of higher current density, higher performance and higher temperature has a det... » read more

How To Make Autonomous Vehicles Reliable


The number of unknowns in automotive chips, subsystems and entire vehicles is growing as higher levels of driver assistance are deployed, sparking new concerns and approaches about how to improve reliability of these systems. Advanced Driver Assistance Systems (ADAS) will need to detect objects, animals and people, and they will be used for parking assistance, night vision and collision avoi... » read more

Why Do You Need Chip-Package-System Co-Design And Co-Analysis?


Whether it is the need for sustainable energy, or driving performance while keeping power at bay, or enabling safe and reliable operation of any electronic system, containment of electronic noise — power and signal noise is critical to all of the above. Other factors that impact safe and reliable operation are electromigration (EM), electromagnetic interference (EMI) and mechanical stress ena... » read more

Tackling RF Desense Challenges At The Source


Just imagine you are stepping out of the electronics store with your brand new smart phone. You eagerly scroll down your contacts to dial your best friend and proudly tell them the great news, but as soon as they pick up, your reception is gone! What happened? This problem is commonly described as desense, a degradation of the sensitivity of the receiver due to external noise sources. Desens... » read more

Technologies For Power, Signal, Thermal, And EMI Sign-Off


This paper discusses the challenges associated with designing smaller, faster, and lower cost products. It provides an overview of Apache's power and noise solutions and how these products enable comprehensive chip-package-system convergence flow across multiple design disciplines. To download this white paper, click here. » read more

Optimizing Cost-Performance-Schedule With A Chip-Package-System (CPS) Methodology


To meet smart device requirements with high levels of sophistication from an exceedingly small device running off a battery, the underlying electronics must evolve at a rapid pace. To read more, click here. » read more

Shock Value


By Norman Chang Chip-Package-System (CPS) ESD simulation enables system-wide ESD robustness validation, a common challenge in automotive and aerospace applications. To enable CPS ESD analysis requires an accurate chip electrostatic discharge (ESD) model and a comprehensive system-level ESD methodology. Using an accurate ESD chip model provides the following three benefits. First it helps de... » read more

ANSYS And Apache Technologies For An Integrated Chip-Package-System Flow


This paper presents solutions for effectively managing design specifications (performance) and margins (price). It discusses solutions based on accurate and predictive simulation software from ANSYS and Apache that offers electronics designers a simulation-driven chip–package–system convergence methodology. To download this white paper, click here. » read more