Author's Latest Posts

Accurate Thermal Analysis, Including Thermal Coupling Of On-Chip Hot Interconnect

Driven by rapid advancement in mobile/server computing and automotive/communications, SoCs are experiencing a fast pace of functional integration along with technology scaling. Advanced low power techniques are widely used, while meeting higher performance requirements using a variety of packaging technologies. The Internet of Things (IoT) is further opening up new applications with connected d... » read more

Shock Value

By Norman Chang Chip-Package-System (CPS) ESD simulation enables system-wide ESD robustness validation, a common challenge in automotive and aerospace applications. To enable CPS ESD analysis requires an accurate chip electrostatic discharge (ESD) model and a comprehensive system-level ESD methodology. Using an accurate ESD chip model provides the following three benefits. First it helps de... » read more

New Stacking Issues

Reduced form factors, higher performance, and the demand for lower power necessitate the need for 3D-IC/silicon interposer designs with through-silicon vias (TSVs). That also creates major design challenges in three areas. The verification of power, signal, and reliability integrity—particularly with multi-stacked die on silicon interposer with TSVs—presents issues that can only be overcome... » read more