New Stacking Issues

3D ICs and silicon interposers create challenges for power, signal and reliability verification.


Reduced form factors, higher performance, and the demand for lower power necessitate the need for 3D-IC/silicon interposer designs with through-silicon vias (TSVs). That also creates major design challenges in three areas. The verification of power, signal, and reliability integrity—particularly with multi-stacked die on silicon interposer with TSVs—presents issues that can only be overcome with a new verification methodology that provides accurate modeling and simulation across multiple die and IC package to ensure the success of these designs.

Challenges from the Power Integrity Perspective
Using TSVs in 3D-IC or silicon-interposer designs can cause inter-die noise and other reliability issues. Designing the power delivery network (PDN) to multiple die, passing power from a die that is closer to the package to a die higher in the stack poses power integrity challenges that can be addressed and verified by different methods. A concurrent analysis approach assumes that all the die layout data, including the silicon interposer is available for concurrent simulation. A model-based analysis can be used where some of the die data is not available, for example, from an IP vendor. This approach performs co-analysis of the core die(s) with a generated Chip Power Model (CPM). Assuming that accurate chip power models are used, both methods will produce comparable results, allowing designers to select the method based on the availability of the die(s) layout data.

Reliability and Performance Challenges
Power-related issues can result in thermal and thermal-induced stress failures. IC power, particularly leakage power, is highly temperature-dependent in deep sub-micron VLSI. Increased power density in modern 3D-IC and SiPs presents thermal-induced reliability and performance issues such as electro-migration that must be taken into consideration for system-level designs. One approach to address this challenge is to use a chip thermal model for each die in the 3D-IC/silicon interposer design, including TSV. This Chip Thermal Model (CTM) must include temperature-dependent power, per-layer metal density and self-heating power. By handing off the chip thermal model to the chip-package-system thermal/stress simulation tool for power-thermal co-analysis, designers can accurately and efficiently predict the power and temperature distribution.

Signal Integrity Challenges
From the signal integrity perspective, a problem on jitter noise analysis for Wide-I/O applications has surfaced for silicon interposer designs. Apart from the traditional SSO between package and board, the wide-I/O communication channel lays on the silicon interposer, where accurate RLCK channel extraction is needed with consideration for TSV modeling. The number of bits on a typical Wide-I/O design can span from 1K to 8K bits in a parallel bus on the silicon interposer, which can introduce significant jitter due to simultaneous switching. A comprehensive system-level SSO solution for jitter analysis needs to consider the driver/receiver on different chips, as well as the parallel bus channel on the silicon interposer in a package.

To help ensure a timely and successful design tape-out, the 3D-IC/silicon interposer designs necessitate a comprehensive chip-package-system (CPS) methodology, allowing designers to mitigate the power, noise, and reliability issues.


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