Author's Latest Posts

SLAM And DSP Implementation
By Cadence - 29 May, 2019 - Comments: 0

With the introduction of simultaneous localization and mapping technology, or SLAM, there comes a need for more sophisticated DSPs to handle the required computations. To address this need, Cadence has introduced the Tensilica Vision Q7 DSP to handle the requirements of SLAM, including high performance, low power, and with an ease of development that engineers can leverage to design new and exc... » read more

Automotive Functional Safety Using LBIST and Other Detection Methods
By Cadence - 24 Apr, 2019 - Comments: 0

Functional safety requirements for safety-critical applications are addressed with the insertion of safety mechanisms to detect and/or correct potential failures: their effectiveness is measured by diagnostic coverage (DC). Built-in-self-test, or BIST, originally developed for manufacturing test, can be used as a detection mechanism for functional safety. However, it requires original values to... » read more

Delivering Superior Throughput For EDA Verification Workloads
By Cadence - 27 Mar, 2019 - Comments: 0

Perhaps no industry is more competitive than modern electronics manufacturing and chip design. As consumers, we take it for granted that electronic devices continue to get faster, cheaper, and more capable with each generation. From smart watches to industrial controls to electronic heart-rate monitors, electronics manufacturers are challenged to build smarter, more complex devices leveraging s... » read more

Unified Compression and LBIST in a Physically Aware Environment
By Cadence - 27 Feb, 2019 - Comments: 0

Unified compression is a new approach that unifies scan compression and logic built-in self-test (LBIST). It leverages recent innovations from Cadence in physically-aware design for test (DFT) to solve routing congestion and area issues from traditional discrete approaches and delivers a confident path to high-quality test. On a sample design, area savings of 35–47%, and scan wirelength savin... » read more

Developing Smarter, Safer Cars with ADAS IP
By Cadence - 16 Jan, 2019 - Comments: 0

By Charles Qi, Sr. Design Engineering Architect, and Neil Robinson, Product Marketing Director, IP Group, Cadence Today’s cars are a full-fledged electronic system on wheels, where every part is interrelated and must be designed, optimized, and verified simultaneously. As a result, it’s important to apply a holistic approach when developing automotive systems, taking into consideration t... » read more

Consolidating RF Flow for High-Frequency Product Design
By Cadence - 09 Jan, 2019 - Comments: 0

Design flows are currently fragmented due to the use of poorly connected EDA tools for various design tasks. Fragmented flows are unable to meet new challenges such as increased system and circuit complexity, stricter bandwidth requirements, smaller device sizes, and changing packaging needs. In this white paper, we look at how the Cadence Virtuoso RF Solution provides a single, well-integrated... » read more

Enabling Embedded Vision Neural Network DSPs
By Cadence - 19 Dec, 2018 - Comments: 0

Neural networks are now being developed in a variety of technology segments in the embedded market, from mobile to surveillance to the automotive segment. The computational and power requirements to process this data is increasing, with new methods to approach deep learning challenges emerging every day. Vision processing systems must be designed holistically, for all platforms, with hardwa... » read more

Reducing Latency, Power, and Gate Count with Floating-Point FMA
By Cadence - 12 Dec, 2018 - Comments: 0

Today’s digital signal processing applications such as radar, echo cancellation, and image processing are demanding more dynamic range and computation accuracy. Floating-point arithmetic units offer better precision, higher dynamic range, and shorter development cycles when compared with fixed-point arithmetic units. Minimizing the design’s time to market is more important than ever. Algori... » read more

Delivering Superior Throughput For EDA Verification Workloads
By Cadence - 28 Nov, 2018 - Comments: 0

Perhaps no industry is more competitive than modern electronics manufacturing and chip design. As consumers, we take it for granted that electronic devices continue to get faster, cheaper, and more capable with each generation. From smart watches to industrial controls to electronic heart-rate monitors, electronics manufacturers are challenged to build smarter, more complex devices leveraging s... » read more

Delivering Superior Throughput for EDA Verification Workloads
By Cadence - 07 Nov, 2018 - Comments: 0

Perhaps no industry is more competitive than modern electronics manufacturing and chip design. As consumers, we take it for granted that electronic devices continue to get faster, cheaper, and more capable with each generation. From smart watches to industrial controls to electronic heart-rate monitors, electronics manufacturers are challenged to build smarter, more complex devices leveraging s... » read more

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