Author's Latest Posts

Fixed and Floating FMCW Radar Signal Processing with Tensilica DSPs
By Cadence - 04 Dec, 2019 - Comments: 0

Automotive advanced driver assistance system (ADAS) applications increasingly demand radar modules with better capability and performance. These applications require sophisticated radar processing algorithms and powerful digital signal processors (DSPs) to run them. Because these embedded systems have limited power and cost budgets, the DSP’s instruction set architecture (ISA) needs to be eff... » read more

Compressing Datasets Created During Silicon Design
By Cadence - 23 Oct, 2019 - Comments: 0

Authors: Guru Rao, Distinguished Engineer; Shakir Abbas, Software Engineering Group Director; Mohammad Mirfendereski, Configuration Management Architect; Cadence. Harsh Sharangpani, CEO and CTO; Rajesh Patil, VP-Business Development; Ascava. During the design cycle for modern semiconductor components, a very large amount of data is generated and stored, often accumulating to hundreds of tera... » read more

Celsius Thermal Solver
By Cadence - 25 Sep, 2019 - Comments: 0

The Celsius Thermal Solver environment enables all aspects of thermal analysis to quickly and accurately identify thermal problems in IC packages, PCBs, and electronics systems. It features an innovative massive parallel solver technology that enables simulation speeds up to 10 times faster than conventional thermal simulators, with significantly reduced memory usage. It includes a powerful fin... » read more

A Complete System-Level Security Verification Methodology
By Cadence - 04 Sep, 2019 - Comments: 0

Hardware is at the root of all digital systems, and security must be considered during the system-on-chip (SoC) design and verification process. Verifying the security of an SoC design is challenging because of time to market pressure and resource constraints. Resources allocated to the already time-consuming task of functional verification must be diverted to security verification, which requi... » read more

Improving Simulation Throughput Using The Xcelium Parallel Logic Simulator
By Cadence - 26 Jun, 2019 - Comments: 0

Simulators have been around for a long time. First, there were interpreters in the ‘80s and ‘90s, and despite being relatively slow, they were a big step up from fabricating the design and hoping it worked. However, as designs continued to increase in size, the interpreters could not keep up with simulation needs, and innovation was required for simulators to keep pace with new technology. ... » read more

Revolution By Evolution: Getting To The Next Technology Breakthrough In Analog Simulation
By Cadence - 12 Jun, 2019 - Comments: 0

Recent technology developments, advanced-node adoptions, and Moore than Moore designs have forced analog and custom IC designers to adopt new design practices that benefit from these advancements. These changes have resulted in the need to simulate larger designs with more post-layout parasitics. In addition, many custom IC designs such as flash memory, MRAM, sensor arrays, etc., now require SP... » read more

SLAM And DSP Implementation
By Cadence - 29 May, 2019 - Comments: 0

With the introduction of simultaneous localization and mapping technology, or SLAM, there comes a need for more sophisticated DSPs to handle the required computations. To address this need, Cadence has introduced the Tensilica Vision Q7 DSP to handle the requirements of SLAM, including high performance, low power, and with an ease of development that engineers can leverage to design new and exc... » read more

Automotive Functional Safety Using LBIST and Other Detection Methods
By Cadence - 24 Apr, 2019 - Comments: 0

Functional safety requirements for safety-critical applications are addressed with the insertion of safety mechanisms to detect and/or correct potential failures: their effectiveness is measured by diagnostic coverage (DC). Built-in-self-test, or BIST, originally developed for manufacturing test, can be used as a detection mechanism for functional safety. However, it requires original values to... » read more

Delivering Superior Throughput For EDA Verification Workloads
By Cadence - 27 Mar, 2019 - Comments: 0

Perhaps no industry is more competitive than modern electronics manufacturing and chip design. As consumers, we take it for granted that electronic devices continue to get faster, cheaper, and more capable with each generation. From smart watches to industrial controls to electronic heart-rate monitors, electronics manufacturers are challenged to build smarter, more complex devices leveraging s... » read more

Unified Compression and LBIST in a Physically Aware Environment
By Cadence - 27 Feb, 2019 - Comments: 0

Unified compression is a new approach that unifies scan compression and logic built-in self-test (LBIST). It leverages recent innovations from Cadence in physically-aware design for test (DFT) to solve routing congestion and area issues from traditional discrete approaches and delivers a confident path to high-quality test. On a sample design, area savings of 35–47%, and scan wirelength savin... » read more

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