Author's Latest Posts

Accelerating DO-254 Approval
By Cadence - 23 Nov, 2016 - Comments: 0

This white paper explores software tools as they relate to meeting the DO-254 Design Assurance Guidance for Airborne Electronic Hardware specifications, and what steps must be performed in order to use your typical design automation tools such as simulation, synthesis, etc. In this paper, we will explore how DO-254 views tools, learn which tools receive the highest scrutiny and why, and how to ... » read more

Using High-Level Synthesis To Design And Verify 802.11ah Baseband IP
By Cadence - 09 Nov, 2016 - Comments: 0

The proposed IEEE 802.11ah wireless networking protocol is designed to meet the requirements of Internet of Things (IoT) connectivity, providing the bit rate, security, and low power required for these types of connected devices. Design requirements for 802.11ah access point and clients vary widely, even though all implement the same mathematical algorithm. In this paper, we will discuss how... » read more

Massively Parallel Electrically Aware Design
By Cadence - 26 Oct, 2016 - Comments: 0

In-design verification is opening new opportunities to shorten design cycles and maximize circuit performance. Whereas physical verification has traditionally required a tradeoff between accuracy and performance for larger designs, recent advances in large-scale distributed computing may offer an alternative. Cloud infrastructure needs are pushing the industry toward larger multi-core server ar... » read more

Addressing Memory Characterization Capacity And Throughput Requirements With Dynamic Partitioning
By Cadence - 12 Oct, 2016 - Comments: 0

Typical memory characterization techniques using memory compilers and instance-specific memories have a number of tradeoffs—development time, accuracy, performance, and more. Ad-hoc instance-specific characterization methods such as dynamic simulation, transistor-level static timing analysis, and divide-and-conquer suffer from multiple limitations that prohibit usage for 40nm technologies and... » read more

How High-Level Synthesis Was Used To Develop An Image-Processing IP Design From C++ Source Code
By Cadence - 28 Sep, 2016 - Comments: 0

Imagine working long and hard on a design, only to learn that you need to add new (and more complex) functionality a few months before your targeted tapeout. How can you deliver the performance and capabilities expected in the same timeframe? For Bosch, high-level synthesis (HLS) provided the solution. In this paper, we will discuss how HLS technology enabled the team to meet an aggressive sche... » read more

Accelerating Monte Carlo Analysis At Advanced Nodes
By Cadence - 10 Aug, 2016 - Comments: 0

Advanced-node designs have much larger variation, making it much more difficult to achieve high yields at these processes. But can you really afford to run thousands or even millions of statistical simulations to predict how well your design will meet its specs? Or overdesign to accommodate manufacturing variations? In this paper, we will introduce a fast Monte Carlo analysis technique that del... » read more

Automating Inter-Layer In-Design Checks In Rigid-Flex PCBs
By Cadence - 27 Jul, 2016 - Comments: 0

Flexible PCBs (flex/rigid-flex) make it possible to create a variety of products that require small form factors and light weight, such as wearable, mobile, military, and medical devices. As flexible PCB fabrication technology has matured in response to demands for smaller, lighter products, new design challenges have emerged. This paper discusses some of the key challenges to address and also ... » read more

Addressing Process Variation And Reducing Timing Pessimism At 16nm And Below
By Cadence - 13 Jul, 2016 - Comments: 0

At 16nm and below, on-chip variation (OCV) becomes a critically important issue. Increasing process variation makes a larger impact on timing, which becomes more pronounced in low-power designs with ultra-low voltage operating conditions. In this paper, we will discuss how a new methodology involving more accurate library characterization and variation modeling can reduce timing margins in libr... » read more

Addressing The Challenges Of Photonic IC Design Via An Integrated Electronic/Photonic Design Automation Environment
By Cadence - 11 May, 2016 - Comments: 0

Photonics—the science and technology of generating, controlling, and detecting light—is transitioning quickly into mainstream electronic designs. Photonic IC (PIC) design does, however, come with some unique challenges in areas including layout, error checking, and circuit modeling. While electronic designers would have expertise in using a traditional electronic design automation (EDA) flo... » read more

Plan-Based Analog Verification Methodology
By Cadence - 27 Apr, 2016 - Comments: 0

The ability to verify all the aspects of an analog design and to keep track of all the different verification tasks is a growing challenge. Manual attempts to do so often lead to mistakes since they rely on constantly updated documents. The Cadence Virtuoso ADE Verifier provides an overarching verification plan that links to all analog tests across multiple designers. The Virtuoso ADE Verifie... » read more

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