Random walk-based solvers can provide accurate parasitic extraction for sophisticated use models, allowing design teams to improve processing performance.
In-design verification is opening new opportunities to shorten design cycles and maximize circuit performance. Whereas physical verification has traditionally required a tradeoff between accuracy and performance for larger designs, recent advances in large-scale distributed computing may offer an alternative. Cloud infrastructure needs are pushing the industry toward larger multi-core server architectures and massively parallel computing frameworks. To address the larger designs necessary for today’s market, massively parallel computing frameworks and in-design-based parallel extraction, enabled through tools such as Cadence Virtuoso Layout Suite for Electrically Aware Design (EAD), will allow random walk-based solvers to provide accurate parasitic extraction to support more sophisticated use models and enable better optimization and faster processing.
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Slowdown due to impact on timing, and dependencies between power, thermal and timing that may not be caught by signoff tools.
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SoC bandwidth, integration expand as data centers use more FPGAs for machine learning.
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Problems won’t derail next-gen litho, but could limit use and affect schedules.
AI-enabled systems are being designed to process more data locally as device scaling benefits decline.
Access to source code makes it attractive for custom applications, but gaps remain in the tool flow and in software.
Growing volume of data and limited improvements in performance create new opportunities for approaches that never got off the ground.
What happens when companies are combined? The outcome often isn’t as good as the announcement.
As complexity and device sizes rise, so does the need for an on-chip network.
Experts at the Table, part 1: Are we looking to solve the wrong problems? Where does parallelization work best and why.
Synopsys Co-CEO Aart de Geus explains why systemic complexity will be the next big challenge, and what that means for EDA and the chip industry.
IP reuse has reduced the urgency for a higher level of abstraction in complex system-level design, but that still could change.
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