Random walk-based solvers can provide accurate parasitic extraction for sophisticated use models, allowing design teams to improve processing performance.
In-design verification is opening new opportunities to shorten design cycles and maximize circuit performance. Whereas physical verification has traditionally required a tradeoff between accuracy and performance for larger designs, recent advances in large-scale distributed computing may offer an alternative. Cloud infrastructure needs are pushing the industry toward larger multi-core server architectures and massively parallel computing frameworks. To address the larger designs necessary for today’s market, massively parallel computing frameworks and in-design-based parallel extraction, enabled through tools such as Cadence Virtuoso Layout Suite for Electrically Aware Design (EAD), will allow random walk-based solvers to provide accurate parasitic extraction to support more sophisticated use models and enable better optimization and faster processing.
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Steps are being taken to minimize problems, but they will take years to implement.
But that doesn’t mean it’s going to be mainstream anytime soon.
Companies are speeding ahead to identify the most production-worthy processes for 3D chip stacking.
New capacity planned for 2024, but production will depend on equipment availability.
Number of options is growing, but so is the list of tradeoffs.
Increased transistor density and utilization are creating memory performance issues.
Suppliers are investing new 300mm capacity, but it’s probably not enough. And despite burgeoning 200mm demand, only Okmetic and new players in China are adding capacity.
The industry reached an inflection point where analog is getting a fresh look, but digital will not cede ground readily.
100% inspection, more data, and traceability will reduce assembly defects plaguing automotive customer returns.
Engineers are finding ways to effectively thermally dissipate heat from complex modules.
Different interconnect standards and packaging options being readied for mass chiplet adoption.
Steps are being taken to minimize problems, but they will take years to implement.
Disaggregation and the wind-down of Moore’s Law have changed everything.
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