Rob Eccles

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Rob Eccles is a field applications engineer at Calypto Design Systems.

Author's Latest Posts

Power Reduction At RTL: Data Gating Adders And Multipliers
By Rob Eccles - 20 Apr, 2015 - Comments: 0

In our previous blog, “Low Power Paradox”, we discussed the implications of the move to FinFET technology. Dynamic power is dominant in finFET designs. Several techniques are available to reduce dynamic power consumption. Microarchitecture changes are one method and they can result in significant power savings. One technique that is frequently used is the data gating of adders and m... » read more

A Survey Of Our Low Power Blogs In 2014
By Rob Eccles - 12 Dec, 2014 - Comments: 0

Over the past year, we have written a number of blogs on low power IC design. Here at the end of 2014 approaches, let’s look back at what we have discussed Our blogs covered methods to estimate and reduce power consumption in digital ICs. Our recommendation is that you do this early in the design cycle, such as the RTL coding stage, when you can have the most positive impact. In the first... » read more

Memory Gating Power Optimizations
By Rob Eccles - 07 Nov, 2014 - Comments: 0

Saving power in SOCs is challenging. Often there are many memories, which collectively can consume a significant amount of power, compelling designers to make architectural choices to minimize power. These require a fair amount of study and may impact functionality and/or embedded software. Fortunately, memory gating can save power without impacting the architecture or the software. The... » read more

Making Accurate Power Estimates At RTL
By Rob Eccles - 14 Oct, 2014 - Comments: 0

It may seem counterintuitive, but an accurate estimation of power at Register Transfer Level can be made. In this blog, we will learn how it can be done. The main ingredient In order to understand RTL power estimation, let us first consider making the power estimation at gate level. At gate level we have a netlist that contains standard cell instances. These standard cells have been charact... » read more

Creating A Strategy For Power Reduction In ICs
By Rob Eccles - 07 Aug, 2014 - Comments: 0

In last month’s blog, various power saving techniques were presented. These different techniques fit into three categories: gross (or coarse-grain) design, fine-grain design, and fine-grain process. In this blog, different techniques will be compared. By understanding the different techniques, it will become clear which ones to use in your design. Fine-grain process techniques For ... » read more

Switching Activity And The Unknown
By Rob Eccles - 10 Apr, 2014 - Comments: 0

Switching activity is essential to measuring power in digital circuits, and it is also important for optimizing digital designs. Power can be static, caused by leakage, or dynamic, caused by switching. Switching activity is crucial because dynamic power is, after all, proportional to the switching activity in the design. Definition Switching activity is the measurement of changes of signal ... » read more

Verifying Power Optimized Designs Using Sequential Analysis
By Rob Eccles - 16 Jan, 2014 - Comments: 0

All power optimization tools can perform combinational optimization, where there is an opportunity to gate a register clock input, based on the combinational logic that is feeding the register’s data input. While this method works well and does not alter the logic behavior at the register, the problem is that it leaves additional power saving opportunities on the table. However, sequential... » read more

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