Memory Gating Power Optimizations

A look at the different types of power optimizations for memories.


Saving power in SOCs is challenging. Often there are many memories, which collectively can consume a significant amount of power, compelling designers to make architectural choices to minimize power. These require a fair amount of study and may impact functionality and/or embedded software. Fortunately, memory gating can save power without impacting the architecture or the software.

There are a number of different methods of power optimization for memories. Some rely on partial or complete power-down features designed into the memory, while others are applicable to all memories.

The ability to analyze the design across register boundaries is important to find all possible power saving optimizations.

Redundant write
Sometimes a write operation can happen on consecutive cycles without a change in data or address. These are redundant writes. When these occur on consecutive cycles, memory operations can be disabled for all but one of them by gating the clock, the memory enable, or the chip select pin.

Redundant read
A similar optimization is available for redundant read operations. When there are consecutive reads with the same address, the memory needs to operate for only one cycle. When this occurs, the memory can be gated.

Stability optimizations
When a memory is inactive, this means that the data outputs are not changing. In other words, the outputs are stable. As such, stability optimizations can be applied to the logic downstream of the memory.

Other observability optimizations
The redundant read and write conditions are examples of applying an “observability don’t care” (ODC) to a memory. There are other situations where there is an ODC on memory inputs. One example is when pipelined data has a valid signal. This valid signal indicates whether the data is valid or invalid for a particular cycle. When the data is invalid, it does not need to be written to memory, and an ODC occurs. Similar situations can apply to address, read/write, etc.

Light and deep sleep modes
Generally, light and deep sleep refer to the time required to enter and exit sleep. Most memories can exit light sleep in a single cycle. Expect deep sleep to take multiple cycles to restore operation.

Implementation of sleep modes varies. A sleep mode may involve shutdown of the periphery and/or a partial power-down of the array. Generally, sleep modes preserve the data in the memory. For more information about the implementation and timing of your memories, consult the designer or the vendor of the memory IP.

Light sleep optimizations
To find a light sleep optimization, a number of consecutive cycles of inactivity need to be identified. Inactivity can be redundant reads, redundant writes, or inactive memory enable pins.

To identify multiple cycles of inactivity in the logic, it is necessary to analyze across register boundaries between the memory and the design’s primary inputs. Examining the design across register boundaries is called sequential analysis — this is essential to effective memory gating.

Deep sleep optimizations
Deep sleep mode is implemented by the RTL designer. It is normally invoked from a register under software control that has its output connected to the deep sleep pin on the memory.

Memory shutdown optimizations
Finally, a memory can be completely shut down. In this case, the memory states are lost.

As with deep sleep, this is not implemented in current tools automatically. It is typically invoked from a register that may be set/reset under software control that is driving the memory’s shutdown pin.

When it comes to the number of power saving strategies using memory gating, most of these techniques can be applied automatically with a memory gating tool. The other modes are architectural and are driven by software control.

For the optimizations that can be applied automatically, deep sequential analysis is used to identify the memory gating opportunities. This is necessary because the scenarios involve multiple cycles of activity and because the optimization logic needs to be activated and deactivated over multiple cycles.

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