A Survey Of Our Low Power Blogs In 2014

Over the past year, we have written a number of blogs on low power IC design. Here at the end of 2014 approaches, let’s look back at what we have discussed Our blogs covered methods to estimate and reduce power consumption in digital ICs. Our recommendation is that you do this early in the design cycle, such as the RTL coding stage, when you can have the most positive impact. In the first... » read more

Memory Gating Power Optimizations

Saving power in SOCs is challenging. Often there are many memories, which collectively can consume a significant amount of power, compelling designers to make architectural choices to minimize power. These require a fair amount of study and may impact functionality and/or embedded software. Fortunately, memory gating can save power without impacting the architecture or the software. The... » read more

Start Early, Cover All The Bases

Design for low power always has challenged designers and design tools. You need to have accuracy, because you are estimating implementation-centered parameters, but you need to start early, before implementation, if you are to have any hope of meaningfully reducing power. Sure, you can always play with body-bias, but that is a crude control. Real reductions after architecture always come throug... » read more