Power Reduction At RTL: Data Gating Adders And Multipliers

What low-power techniques to use when, and why you need to know this.

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In our previous blog, “Low Power Paradox”, we discussed the implications of the move to FinFET technology.

Dynamic power is dominant in finFET designs. Several techniques are available to reduce dynamic power consumption. Microarchitecture changes are one method and they can result in significant power savings.

One technique that is frequently used is the data gating of adders and multipliers. This technique is sometimes identified by the power optimization tool, but the implementation details are left to the designer.

Adders and multipliers can consume significant amounts of combinational power within a design. (In this discussion, we will consider only the adders and multipliers that are purely combinational; i.e., they contain no flip-flops.) Often most of the energy consumed by the adder and/or multiplier is wasted because the adder or multiplier output is not used (or observed).

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In this example schematic, the multiplier is feeding a multiplexer data input. Depending on the state of the multiplexer select input (sel), the multiplier data output may be unobservable. So, if we can stop the multiplier from switching while it is not observed, then we can save some power.

An observant design engineer may discover this power-saving opportunity, or it may be obtained from a power optimization tool. In our example, the power optimization tool needs to look across register boundaries, so sequential analysis is required.

The power optimization tool has given the signal “sel” as the data gating expression, which can be implemented in one of three ways: AND gates, OR gates, or latches.

Choosing between these options depends on the switching activity in the design. If the periods of non-observability are often only a single cycle, latches might be best.

Gates are small and consume less power than latches. Of course, when the gates’ output switches, we get additional switching activity. This can be acceptable if there are multi-cycle, contiguous periods of non-observability.

For the cases where there are many single cycle non-observable periods, using latches might be preferred. The problem is that latches themselves consume more power than gates, as we’ve already noted, but they reduce switching more than simple gates. So even though a latch consumes more power itself, it may reduce power overall by reducing more switching activity in the combinatorial logic than simple gates.

It can be difficult to predict whether latches or gates are preferred. When in doubt, you can simulate both to see which consumes less power.

If you have decided to use gates instead of latches, then you will need to choose between AND and OR gates. The answer to this problem lies again in the switching activity data. A rule of thumb is that if the probability of the inputs is less than 1/2, then use AND. If the probability of the inputs is more than ½, use OR. This probability information can be obtained from the power optimization tool.

Used properly, this kind of modification can significantly reduce the power in your design. Still, the question from our last blog still remains. Who in the project team is in the best position to make these kinds of tradeoffs for power reduction?