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The New Deep Learning Memory Architectures You Should Know About
By eSilicon - 21 Mar, 2018 - Comments: 0

Artificial intelligence (AI) has come a long way. While our parents grew up with the dream to one day roam with robots, today we are interviewing Sophia, a citizen of Saudi Arabia, who is also the first humanoid robot to be granted a citizenship in any country. Deep learning, a brain-inspired discipline of AI has been around for a long time but has only recently taken off due to abundant data, ... » read more

eSilicon Builds ASIC Business On Leading-Edge Chip Design
By eSilicon - 21 Feb, 2018 - Comments: 0

How advanced application specific integrated circuits (ASIC) chip design and manufacturing for leading-edge applications such as networking and artificial intelligence can be successfully outsourced. The company which has capabilities in 2.5D packaging, high-bandwidth memories (HBM), and silicon IP for fast memories and SerDes designs. The company has many leading system companies as custome... » read more

eSilicon Builds ASIC Business On Leading-Edge Chip Design
By eSilicon - 24 Jan, 2018 - Comments: 0

This paper explores how advanced application specific integrated circuits (ASIC) chip design and manufacturing for leading-edge applications such as networking and artificial intelligence can be successfully outsourced. The company we profile is eSilicon, which has capabilities in 2.5D packaging, high-bandwidth memories (HBM), and silicon IP for fast memories and SerDes designs. The company ha... » read more

When The Chips Are Down, Software-Defined Data Centers Can Ease R&D Creases
By eSilicon - 26 Jul, 2017 - Comments: 0

The design team of a fabless semiconductor company seemed to go into a tizzy every 6 months. They had to deliver the latest chips to their end customer amid extremely aggressive deadlines. They realized that if they needed the might of the millennials to bump up their bottom line, they would have to give their models and designs a makeover (read upgrade) every few months. To read more, click... » read more

Start Your HBM/2.5D Design Today
By eSilicon - 28 Jun, 2017 - Comments: 0

High-bandwidth memory (HBM) is a JEDEC-defined standard, dynamic random access memory (DRAM) technology that uses through-silicon vias (TSVs) to interconnect stacked DRAM die. In its first implementation, it is being integrated with a system-on-chip (SoC) logic die using 2.5D silicon interposer technology. In June 2015, AMD introduced its Fiji processor, the first HBM 2.5D design, which comp... » read more

Why Is TCAM Essential For The Cloud?
By eSilicon - 27 Apr, 2017 - Comments: 0

With port speeds exceeding 100Gbps, route lookups that are fundamental to all routers have relied on ternary content addressable memories (TCAMs) to provide a lookup response within a clock cycle. However, TCAMs in discrete form are expensive, consume a lot of power, compete for precious real estate on the printed circuit board (PCB), and often lack required flexibility. Embedding a TCAM block ... » read more

Optimal Memory Strategies: Where HBM2 Fits
By eSilicon - 23 Mar, 2017 - Comments: 0

How are you going to build your next big product? Whether it’s in the networking, wireless, mobile or computing market, you are now increasing the functionality of your product. It needs to be able to do many tasks – fast, at low power, and pack as much functionality into the tiniest area for cost effectiveness. What does this mean for the embedded memory content? It is growing rapidly. ... » read more

Find The Best IP For You
By eSilicon - 26 Oct, 2016 - Comments: 0

It can be quite challenging and time consuming to find the right semiconductor IP for your project. You’ve got to find IP that does not consume too much power, meets your performance target, has the lowest leakage when your product goes on standby, and last but not least, IP that occupies the least amount of expensive real estate on your chip. How can you accomplish such a task without having... » read more

High-Bandwidth Memory
By eSilicon - 27 Apr, 2016 - Comments: 0

High-bandwidth memory (HBM) is a JEDEC-defined standard, dynamic random access memory (DRAM) technology that uses through-silicon vias (TSVs) to interconnect stacked DRAM die. In its first implementation, it is being integrated with a system-on-chip (SoC) logic die using 2.5D silicon interposer technology. This white paper explains HBM’s value proposition, and how these five companies make... » read more

Design Virtualization And Its Impact On SoC Design
By eSilicon - 27 May, 2015 - Comments: 0

At advanced technology nodes (40nm and below), the number of options that a system-on-chip (SoC) designer faces is exploding. Choosing the correct combination of these options can have a dramatic impact on the quality, performance, cost and schedule of the final SoC. Using conventional design methodologies, it is very difficult to know if the correct options have been chosen. There is simply ... » read more

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