Author's Latest Posts


Growing Challenges With Wafer Bump Inspection


As advanced packaging goes mainstream, ensuring that wafer bumps are consistent has emerged as a critical concern for foundries and OSATs. John Hoffman, computer vision engineering manager at CyberOptics, talks about the shift toward middle-of-line and how that is affecting inspection and metrology, why there is so much concern over co-planarity and alignment, how variation can add up and creat... » read more

Don’t Toss That Gasoline Engine Just Yet


As auto makers race toward increasingly electrified vehicles, there is an entire after-market effort underway that was started decades ago, largely by hobbyists. And after decades of playing around with batteries and novel technologies, they've come to roughly the same conclusions as the owners of newer electric vehicles. There are definite advantages as well as some limitations, and the needle... » read more

Open Cavity Plastic Packaging


Rapid change in electronics is also causing rapid obsolescence. But in some markets, the systems are supposed to last for decades. Sam Sadri, senior process engineer at QP Technologies (formerly Quik-Pak), talks with Semiconductor Engineering about why it’s so important to use existing package footprints, what are the challenges in replacing the circuitry inside a package, and which markets a... » read more

Optimizing AI Systems


Inserting AI and machine learning into chips adds a whole new dimension of complexity, and creates a variety of potential problems, including deadlocks, loss of performance, and difficulty in achieving closure on many fronts. Gajinder Panesar, fellow at Siemens EDA, talks with Semiconductor Engineering about what’s changed and how to optimize these new devices and systems by monitoring them f... » read more

EDA Vendors Widen Use Of AI


EDA vendors are widening the use of AI and machine learning to incorporate multiple tools, providing continuity and access to consistent data at multiple points in the semiconductor design flow. While gaps remain, early results from a number of EDA tools providers point to significant improvements in performance, power, and time to market. AI/ML has been deployed for some time in EDA. Still,... » read more

Low-Power Always-On Circuits


Some circuits are always on. A smart phone wakes up when it senses a user, and a smart speaker responds to keywords. The challenge is to make sure these devices don’t consume a lot of power while the rest of a device is powered down, that it remains secure, and that it can quickly wake up whatever other functions are needed. All of this requires a significant amount of engineering work. Amol ... » read more

Building Complex Chips That Last Longer


Semiconductor Engineering sat down to talk about design challenges in advanced packages and nodes with John Lee, vice president and general manager for semiconductors at Ansys; Shankar Krishnamoorthy, general manager of Synopsys' Design Group; Simon Burke, distinguished engineer at Xilinx; and Andrew Kahng, professor of CSE and ECE at UC San Diego. This discussion was held at the Ansys IDEAS co... » read more

Using ML In EDA


Machine learning is becoming essential for designing chips due to the growing volume of data stemming from increasing density and complexity. Nick Ni, director of product marketing for AI at Xilinx, examines why machine learning is gaining traction at advanced nodes, where it’s being used today and how it will be used in the future, how quality of results compare with and without ML, and what... » read more

What’s Changing In DRAM


Most of the attention in chip scaling has been focused on logic and on-chip memory, but off-chip memory is starting to encounter problems, as well. David Fried, vice president of computational products at Lam Research, looks at the impact of shrinking features and increasing density, including variation, thermal effects and aging, as well as effects such as micro-loading and DRAM stacking. » read more

New Approaches For Processor Architectures


Processor vendors are starting to emphasize microarchitectural improvements and data movement over process node scaling, setting the stage for much bigger performance gains in devices that narrowly target what end users are trying to accomplish. The changes are a recognition that domain specificity, and the ability to adjust or adapt designs to unique workloads, are now the best way to impro... » read more

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