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Ed Sperling

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Ed Sperling is the editor in chief of Semiconductor Engineering.

Author's Latest Posts

Toward Software-Defined Vehicles
By Ed Sperling - 24 Jul, 2024 - Comments: 0

Speed is everything when it comes to designing automotive electronics, but not in the usual way. In the past, product cycles often lasted five to seven years, from initial design to implementation inside of vehicles. That no longer works as vehicles adopt more electronic features to replace mechanical ones, and as competition heats up over the latest features and nearly instantaneous over-the-a... » read more

Managing kW Power Budgets
By Ed Sperling - 17 Jul, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss increasing power demands and how to address it with Hans Yeager, senior principal engineer, architecture, at Tenstorrent; Joe Davis, senior director for Calibre interfaces and EM/IR product management at Siemens EDA; Mo Faisal, CEO of Movellus; Trey Roessig, CTO and senior vice president of engineering at Empower Semiconductor.... » read more

EDA Revenue Up, China Weak
By Ed Sperling - 15 Jul, 2024 - Comments: 0

EDA and hardware IP revenue grew 14.4% to $4.522 billion in Q1, extending a streak that began several years ago with unabated double-digit growth. But the upbeat report masked a sharp sales drop in China for reasons that have yet to be determined. Revenue in the overall Asia/Pacific region grew a healthy 19% YoY, while China was -6.3%. The negative impact was offset by new strength in India,... » read more

Intel Vs. Samsung Vs. TSMC
By Ed Sperling - 15 Jul, 2024 - Comments: 3

The three leading-edge foundries — Intel, Samsung, and TSMC — have started filling in some key pieces in their roadmaps, adding aggressive delivery dates for future generations of chip technology and setting the stage for significant improvements in performance with faster delivery time for custom designs. Unlike in the past, when a single industry roadmap dictated how to get to the next... » read more

Changes In Formal Verification
By Ed Sperling - 11 Jul, 2024 - Comments: 0

For the better part of two decades, formal verification was considered too difficult to use in many designs and too slow for anything but narrow bug hunting. Much has changed recently. Ashish Darbari, CEO of Axiomise, explains why formal is now essential for finding deadlocks, security holes, and Xprop issues in mission-critical, safety-critical, and AI designs, and how that will apply to chipl... » read more

Promises And Pitfalls Of SoC Restructuring
By Ed Sperling - 12 Jun, 2024 - Comments: 0

As chips become more complex and increasingly heterogeneous, it's becoming more difficult to keep track of different methodologies, tools, and blend data from different sources to create a chip. Tim Schneider, staff application engineer at Arteris, explains why IP-XACT has become so critical, why it took so long to gain a solid foothold in chip design, and how the new IP-XACT standard interface... » read more

Making Adaptive Test Work Better
By Ed Sperling - 10 Jun, 2024 - Comments: 0

One of the big challenges for IC test is making sense of mountains of data, a direct result of more features being packed onto a single die, or multiple chiplets being assembled into an advanced package. Collecting all that data through various agents and building models on the tester no longer makes sense for a couple reasons — there is too much data, and there are multiple customers using t... » read more

MCU Changes At The Edge
By Ed Sperling - 03 Jun, 2024 - Comments: 0

Microcontrollers are becoming a key platform for processing machine learning at the edge due to two significant changes. First, they now can include multiple cores, including some for high performance and others for low power, as well as other specialized processing elements such as neural network accelerators. Second, machine learning algorithms have been pruned to the point where inferencing ... » read more

Electromigration And IR Drop At Advanced Nodes
By Ed Sperling - 22 May, 2024 - Comments: 0

Manufacturing chips at 3nm and below is a challenge, but it's only part of the problem. Designing chips that can be manufactured and will actually work is potentially an even bigger problem. There is more data to sift through for place-and-route, less margin to pad a design, and there are more physical effects to contend with as transistors get taller, density increases, and chips age. Jeff Wil... » read more

Adapting To Evolving IC Requirements
By Ed Sperling - 07 May, 2024 - Comments: 0

As chip designs become increasingly heterogeneous and domain-specific, packing a device with one-size-fits-all chips or chiplets doesn't make sense. The key is rightsizing different components based on real workloads, so they don't waste power when there is too little utilization of logic, and so they don't struggle to complete tasks because they are undersized. Jayson Bethurem, vice president ... » read more

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