Author's Latest Posts


Revving Up For Edge Computing


The edge is beginning to take shape as a way of limiting the amount of data that needs to be pushed up to the cloud for processing, setting the stage for a massive shift in compute architectures and a race among chipmakers for a stake in a new and highly lucrative market. So far, it's not clear which architectures will win, or how and where data will be partitioned between what needs to be p... » read more

Simultaneous Localization And Mapping


Amol Borkar, senior product manager at Cadence, explains how to track the movement of an object in a scene and how to match features from one image to the next using SLAM. The technology is used in everything from mobile phones to automotive and drones. » read more

Which Verification Engine When


Frank Schirrmeister, group director for product marketing at Cadence, talks about which tools get used throughout the design flow, from architecture to simulation, formal verification, emulation, prototyping all the way to production, how the cloud has impacted the direction of the flow, and how machine learning will impact verification. » read more

Visually Assisted Layout In Custom Design


Avina Verma, group director for R&D in Synopsys’ Design Group, explains why visual feedback and graphical guidance are so critical in complex layouts, particularly for mixed-signal environments. » read more

Disaggregation Of The SoC


The rise of edge computing could do to the cloud what the PC did to the minicomputer and the mainframe. In the end, all of those co-existed (despite the fact that the minicomputer morphed into commodity servers from companies like Dell and HP). What's different this time around is that the computing done inside of those boxes is moving. It is being distributed in ways never considered feasi... » read more

RISC-V Challenges And Opportunities


Semiconductor Engineering sat down to discuss open instruction set hardware and the future of RISC-V with Ben Levine, senior director of product management in Rambus' Security Division; Jerry Ardizzone, vice president of worldwide sales at Codasip; Megan Wachs, vice president of engineering at SiFive; and Rishiyur Nikhil, CTO of Bluespec. What follows are excerpts of that conversation. (L-... » read more

Thermal Challenges And Moore’s Law


Steven Woo, fellow and distinguished inventor at Rambus, looks at the evolution of graphics cards over a couple of decades and how designs changed to deal with more graphics and more heat, and why smaller, faster and cheaper doesn’t apply in this market. » read more

Making Random Variation Less Random


The economics for random variation are changing, particularly at advanced nodes and in complex packaging schemes. Random variation always will exist in semiconductor manufacturing processes, but much of what is called random has a traceable root cause. The reason it is classified as random is that it is expensive to track down all of the various quirks in a complex manufacturing process or i... » read more

Who’s Watching The Supply Chain?


Every company developing chips at the most advanced process nodes these days is using different architectures and heterogeneous processing and memory elements. There simply is no other way to get the kind of power/performance improvements needed to justify the expense of moving to a new process node. So while they will reap the benefits of traditional scaling, that alone is no longer enough. ... » read more

Curvilinear Full-Chip ILT


Leo Pang, chief product officer and executive vice president at D2S, talks about the speed improvements with full-chip inverse lithography technology, why it is so critical in stitching together large chips, and how this approach differs from traditional litho approaches. » read more

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