Author's Latest Posts


Designing An AI SoC


Susheel Tadikonda, vice president of networking and storage at Synopsys, looks at how to achieve economies of scale in AI chips and where the common elements are across all the different architectures. https://youtu.be/fm0kxnj3DuM » read more

The Next Spoiler Alert


Speculative execution seemed like a good idea at the time. As the power/performance benefits of each node shrink began to dwindle, companies like Intel figured out ways to maintain processor speeds at the same or lower power. There were other approaches, as well. Speculative execution and branch prediction are roughly equivalent to pre-fetch in search, which has gotten so good that often the... » read more

The Winograd Transformation


Cheng Wang, senior vice president of engineering at Flex Logix, explains how the Winograd Transformation applies to convolutional neural networks. https://youtu.be/E7QJUby9x-I » read more

New Design Approaches At 7/5nm


The race to build chips with a multitude of different processing elements and memories is making it more difficult to design, verify and test these devices, particularly when AI and leading-edge manufacturing processes are involved. There are two fundamental problems. First, there are much tighter tolerances for all of the components in those designs due to proximity effects. Second, as a re... » read more

Crisis In Data


The push toward data-driven design, debug, manufacturing and reliability holds huge promise, but the big risk is none of this will happen in an organized fashion and everyone will be frustrated. One of the clear messages coming out of DVCon this week is that standards need to be established for data. Even within large chipmakers and systems companies, the data they extract from tools is not ... » read more

New Memory Options


Carlos Macián, eSilicon’s senior director of AI strategy and products, talks about how to utilize memory differently and reduce the movement of data in AI chips, and what impact that has on power and performance. https://youtu.be/wItp6wReVts » read more

Reverse Debug


Chun Chan, product applications engineering director at Synopsys, talks with Semiconductor Engineering about testbench debug and how adding time markers can speed time to signoff. https://youtu.be/tx_89M1bq3Q » read more

The Mighty Sensor In The Fab


The days of scheduled maintenance on fab equipment are coming to an end. In fact, the entire service model as we know it is about to undergo a mammoth change. The addition of more sensors into manufacturing equipment may seem like an evolutionary step, but the impact is going to be much more significant than it might appear. Rather than just alerting fab managers or equipment makers when a p... » read more

Using Sensor Data To Improve Yield And Uptime


Semiconductor equipment vendors are starting to add more sensors into their tools in an effort to improve fab uptime and wafer yield, and to reduce cost of ownership and chip failures. Massive amounts of data gleaned from those tools is expected to provide far more detail than in the past about multiple types and sources of variation, including when and where that variation occurred and how,... » read more

Arms Race In Chip Performance


An AI arms race is taking shape across continents. While this is perilous on many fronts, it could provide a massive boost for the chip technology—and help to solve a long-simmering problem in computing, as well as lots of lesser ones. The U.S. government this week announced its AI Initiative, joining an international scramble for the fastest way to do multiply/accumulate and come up with ... » read more

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