Author's Latest Posts

On The Reverse Breakdown Behavior Of GaAs PIN Diodes For High Power Applications
By Fraunhofer IIS/EAS - 11 Jan, 2023 - Comments: 0

In the field of power electronics, the compound semiconductors gallium nitride and silicon carbide are dominating the market. Due to its beneficial properties, gallium arsenide is gaining more and more importance. The aim is to manufacture devices based on gallium arsenide for use in power electronics with comparable or better properties, but at lower costs. In this work, a first GaAs PIN diode... » read more

Holistic Die-to-Die Interface Design Methodology For 2.5-D Multi-Chip-Module Systems
By Fraunhofer IIS/EAS - 07 Dec, 2022 - Comments: 0

More than Moore technologies can be supported by system level diversification enabled by chiplet based integrated systems within multi-chip-modules (MCM) and silicon interposer based 2.5D systems. The division of large system-on-chip dies into smaller chiplets with different technology nodes specific to the chiplet application requirement enables the performance enhancement at system level whil... » read more

Detection Of Electric Vehicles And Photovoltaic Systems In Smart Meter Data
By Fraunhofer IIS/EAS - 12 Oct, 2022 - Comments: 0

In the course of the switch to renewable energy sources, there is a shift from a few large energy sources (power plants) to a large number of small, distributed energy sources (e.g., photovoltaic systems) and energy storage devices (e.g., electric vehicles). This results in the need to know and identify these energy sources and sinks as soon as new devices are installed, in order to ensure grid... » read more

A Multi-Level Analog IC Design Flow For Fast Performance Estimation Using Template-Based Layout Generators And Structural Models
By Fraunhofer IIS/EAS - 12 Sep, 2022 - Comments: 0

Analog IC design is a very challenging task as essential information is missing in the early design stages. Because the simulation of larger designs is exceedingly computationally expensive at lower abstraction levels, conservative assumptions are usually applied that often result in suboptimal performances such as area and power consumption. In order to enable both early performance estimates ... » read more

Machine Learning-Based Optimization Of Chiral Photonic Nanostructures: Evolution- And Neural Network-Based Design
By Fraunhofer IIS/EAS - 08 Jun, 2022 - Comments: 0

Chiral photonics opens new pathways to manipulate light-matter interactions and tailor the optical response of metasurfaces and -materials by nanostructuring nontrivial patterns. Chirality of matter, such as that of molecules, and light, which in the simplest case is given by the handedness of circular polarization, have attracted much attention for applications in chemistry, nanophotonics and ... » read more

State-Space Model Of An Electro-Mechanical-Acoustic Contactless Energy Transfer System Based On Multiphysics Networks
By Fraunhofer IIS/EAS - 11 May, 2022 - Comments: 0

Contactless energy transfer systems are mainly divided into acoustic, inductive, capacitive and optical, in which main applications are related to biomedical, wireless chargers and sensors in metal enclosures. When solids are used as transfer media, ultrasound transducers based on piezoelectricity can be used for through-wall power transfer, which can be named as electro-mechanical-acoustic con... » read more

A Framework For Ultra Low-Power Hardware Accelerators Using NNs For Embedded Time Series Classification
By Fraunhofer IIS/EAS - 09 Mar, 2022 - Comments: 0

In embedded applications that use neural networks (NNs) for classification tasks, it is important to not only minimize the power consumption of the NN calculation, but of the whole system. Optimization approaches for individual parts exist, such as quantization of the NN or analog calculation of arithmetic operations. However, there is no holistic approach for a complete embedded system design ... » read more

13000 FPS Vision System-on-Chip With Mixed-Signal Compressed Sensing
By Fraunhofer IIS/EAS - 09 Feb, 2022 - Comments: 0

This paper presents a monolithic high-speed VSoC (Vision-System-on-Chip) with three software-programmable 16-bit ASIPs (application-specific instruction-set processors), a 1024-fold column-parallel data path of charge-based convolution functionality, freely configurable A/D conversion, 8-bit processor elements with 128 bytes of RAM each, and asynchronously compressing output of sparse column da... » read more

AI Goes Ultra Low Power — Part 1
By Fraunhofer IIS/EAS - 12 Jan, 2022 - Comments: 0

Based on the concept of the new Federal Agency for Jump Innovations (PSRIN-D), the BMBF initiated three pilot innovation competitions. One of them presented the participants with the task of developing the most energy-efficient AI system possible as a hardware implementation on an ASIC or FPGA. With this, a stack of hundreds of two-minute long ECG signals should be analyzed with a minimum of en... » read more

Design Meets EDA: Gaps And Countermeasures In Analog/Mixed-Signal IC Design
By Fraunhofer IIS/EAS - 08 Dec, 2021 - Comments: 0

Along the path from specification to silicon, the design of analog/mixed-signal chips comprises a variety of challenges. They are of technological, methodological, organizational, communicational, and business nature. Additionally, large gaps are to be managed among the individual challenges. Still up to now, approaches such as the “four eye principle” are used even in industrial practice i... » read more

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