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13000 FPS Vision System-on-Chip With Mixed-Signal Compressed Sensing

A single-chip vision SoC made with a less-expensive classical monolithic integration achieves has good fill factor and competitive performance.

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This paper presents a monolithic high-speed VSoC (Vision-System-on-Chip) with three software-programmable 16-bit ASIPs (application-specific instruction-set processors), a 1024-fold column-parallel data path of charge-based convolution functionality, freely configurable A/D conversion, 8-bit processor elements with 128 bytes of RAM each, and asynchronously compressing output of sparse column data. While 3D integration allows for combining a sensor field in optimal technology with a digital processing chip, it increases chip development, manufacturing and testing costs. In this design, the classical monolithic integration approach is pursued to achieve a single-chip solution with good fill factor and competitive performance in a classical 180 nm 1P6M CIS technology. To demonstrate the advantageous compressed sensing approach for fast and low-latency image processing, an algorithm for laser sheet-of-light triangulation was implemented.

Click here to read more. Fraunhofer document information is here.

 



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