13000 FPS Vision System-on-Chip With Mixed-Signal Compressed Sensing

This paper presents a monolithic high-speed VSoC (Vision-System-on-Chip) with three software-programmable 16-bit ASIPs (application-specific instruction-set processors), a 1024-fold column-parallel data path of charge-based convolution functionality, freely configurable A/D conversion, 8-bit processor elements with 128 bytes of RAM each, and asynchronously compressing output of sparse column da... » read more

Low-Latency Image Acquisition And Processing With A Programmable Vision-System-On-Chip

This work aims to demonstrate the benefits of using a Vision-System-on-Chip for image processing tasks with very high latency demands between image acquisition and processing. By leveraging a column-parallel, mixed-signal data path, which is entirely software-defined by three application-specific instruction- set processors (ASIPs), image data within multiple regions of interest can be analyzed... » read more