Low-Latency Image Acquisition And Processing With A Programmable Vision-System-On-Chip

A method for adding complex vision-based control tasks using a VSoC.


This work aims to demonstrate the benefits of using a Vision-System-on-Chip for image processing tasks with very high latency demands between image acquisition and processing. By leveraging a column-parallel, mixed-signal data path, which is entirely software-defined by three application-specific instruction- set processors (ASIPs), image data within multiple regions of interest can be analyzed at a frame rate of 5 kHz. Thus, with a delay of 0.44ms, the trajectory of a moving object is analyzed and the object is precisely deflected using a solenoid.

To read more, click here.

Leave a Reply

(Note: This name will be displayed publicly)