Chip Aging Becomes Design Problem


Chip aging is a growing problem at advanced nodes, but so far most design teams have not had to deal with it. That will change significantly as new reliability requirements roll out across markets such as automotive, which require a complete analysis of factors that affect aging. Understanding the underlying physics is critical, because it can lead to unexpected results and vulnerabilities. ... » read more

A High-Speed Asynchronous Multi-Input Pipeline For Compaction And Transfer of Parallel SIMD Data


Image sensors with programmable, highly parallel signal processing, so called Vision-Systems-on-Chip, perform computationally intensive tasks directly on the sensor itself. Therefore it is possible to limit the amount of output data to relevant image features only. Reading out such features presents a major challenge, since the position and number of features often is not known. Conventional sy... » read more

The Week In Review: Design


Tools & IP Cadence unveiled its latest DSP for embedded vision and AI, Tensilica Vision Q6 DSP. The DSP is built on a 13-stage processor pipeline and new system architecture designed for use with large local memories, and achieves 1.5GHz peak frequency and 1GHz typical frequency at 16nm. Compared to its predecessor, it offers 1.5X greater vision and AI performance than its predecessor and ... » read more

The Week In Review: Design


Tools Mentor, a Siemens business, filled in the last of the hardware configurations for its Veloce Strato emulation family, creating a full upgrade path. Users can initially purchase only the hardware that they need (StratoTiL) and if later they require more capacity (StratoTi) or the ability to handle larger designs (StratoT), they can incrementally add the necessary hardware to their existin... » read more

Where Is Energy Harvesting?


With power management a top priority in sensor networks, why is energy harvesting—a proven technology with diverse energy sources—conspicuously absent from sensor designs that are the foundation of the Internet of Things? [getkc id="165" kc_name="Energy harvesting"] always has been a promising answer to the limits of battery power. The idea that a device can run for much longer periods o... » read more

The Week In Review: Design


Startup OnScale launched with advanced CAE multi-physics solvers that are seamlessly integrated with a scalable, high performance cloud computing platform built on Amazon's AWS. The company's model is built around a Solver-as-a-Service pay-as-you-go subscription model and targets 5G, IoT/Industrial IoT, biomedical, and autonomous car markets. The company has $3 million in strategic seed fund... » read more

Why Use An Assembly Design Kit And Assembly Design Flow?


A number of years ago, the packages of electronic systems were only intended to protect the circuit from mechanical stresses and to realize a simple fan-out from the close spacing of connections on the circuit to the larger spacing on the packaging. At the time, there were also only a few different packaging types, all of simple design. Over the years, however, the requirements on packages have... » read more

Electronic Design For Reliable Autonomous Driving


In the area of advanced driver assistance systems, most car makers and their suppliers have laid out exciting road maps all the way to highly automated and fully automated driving in 5 to 10 years. But are the electronics keeping up with these ambitious plans? At least for the automotive industry as a mass market, the current design processes for microchips and systems are not yet ready. An ... » read more

Circuit-Level Aging Simulations Predict The Long-Term Behavior Of ICs


Reliability is a major criterion for integrated circuits (ICs) in safety critical applications, such as automotive, medical, or aviation electronics. A particular effect that contributes to wear-out is device (i.e. transistor) degradation. Its impact on the circuit behavior can be verified by circuit level aging simulations, which are offered by various EDA vendors. However, reasonable results ... » read more

Tech Talk: Substrate Noise Coupling


Roland Jancke, head of the department for design methodology for the Fraunhofer's Engineering of Adaptive Systems Division, talks with Semiconductor Engineering about the impact of substrate noise coupling on reliability of chips and how to deal with this issue. https://youtu.be/7E2rCwYr6-o » read more

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