tag: application-specific instruction-set processors

Low-Latency Image Acquisition And Processing With A Programmable Vision-System-On-Chip

By Fraunhofer IIS/EAS - 12 Sep, 2018 - Comments: 0

This work aims to demonstrate the benefits of using a Vision-System-on-Chip for image processing tasks with very high latency demands between image acquisition and processing. By leveraging a column-parallel, mixed-signal data path, which is entirely software-defined by three application-specific instruction- set processors (ASIPs), image data within multiple regions of interest can be analyzed... » read more

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