Geoff Tate

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Geoff Tate is the founder and CEO of Flex Logix. Tate has more than three decades of experience in technology. He is the former CEO of Rambus, and a current board director at Everspin Technologies. He received his BSc in computer science from the University of Alberta, and an MBA from Harvard Business School.

Author's Latest Posts

Introduction To eFPGA Hardware

By Geoff Tate - 01 Feb, 2018 - Comments: 0

Intel builds processor chips and Arm provides processor cores to integrate into chips. Xilinx and Intel (nee Altera) build FPGAs and a range of new startups provide embedded FPGA (eFPGA) to integrate into chips: Achronix, Flex Logix, Menta and QuickLogic. As the diagram above shows, an FPGA chip is a core (the “fabric”) which is surrounded by various kinds of I/O including SERDES,... » read more

The Importance Of Metal Stack Compatibility For Semi IP

By Geoff Tate - 04 Jan, 2018 - Comments: 0

Architects and front end designers usually leave the back end to the physical designers: they know there can be different numbers of metal layers, but may not realize the characteristics of each metal layer may vary layer by layer as well and that different chips use different metal stack ups to optimize for their requirements. This slide from IDF14 shows a simple summary of the breadth of v... » read more

Get eFPGA With Your CPU Now

By Geoff Tate - 07 Dec, 2017 - Comments: 0

eFPGA is available now on mainstream process nodes (40, 28 and 16), in sizes from 200 LUTs to 200K LUTs and with options for DSP and RAM integration to fit almost any customer need. Flex Logix has been working for some time with multiple customers on integrating eFPGA with their CPUs: ARM, RISC-V, Tensilica and others. Bus interfaces include AXI, AHB, APB and TL. Our lead customer has workin... » read more

New Interconnect Makes eFPGA Dense And Portable

By Geoff Tate - 02 Nov, 2017 - Comments: 0

FPGAs were invented over 30 years ago. Today they are much bigger and faster, but their basic architecture remains unchanged: logic blocks formed around LUTs (look-up-tables) in a sea of mesh (x/y grid) interconnect with a matrix of switches at every “intersection.” One FPGA company executive once said they don’t really sell programmable logic, they sell programmable interconnect, beca... » read more

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