Introduction To eFPGA Software

Optimize embedded FPGA designs by using dedicated software tools.


In February, we covered “Introduction to eFPGA Hardware.” Now in April, we’ll provide an introduction to eFPGA software.

An eFPGA is a block of programmable logic from a few thousand to a few hundred thousand LUTs (look up tables) of programmable logic that is embedded in an SoC.

  • The clock(s) for the eFPGA come from the SoC.
  • The configuration of the eFPGA is done by the SoC.
  • And the input pins of the eFPGA are driven from the SoC and the output pins of the eFPGA connect to other blocks of the SoC: the connection can be to a system bus like AXI, to the data/control paths, to memory or to I/O or a combination of all of these.

eFPGA is an “RTL engine”: it is programmed using Verilog or sometimes VHDL and the eFPGA will “execute” the RTL cycle by cycle from inputs through the RTL in the eFPGA to the outputs.

Most eFPGA use a commercial off-the-shelf synthesis tool, most commonly Synposys’ Synplify or occasionally Mentor’s Precision. The synthesis tool reads in the Verilog or VHDL and generates an EDIF file which is a vendor-neutral format based on s-expressions to store electronic netlists.

The EDIF file is then processed by the eFPGA’s own software to do packing, placing, routing, timing generation and then bit file generation. Each eFPGA’s hardware implementation is quite different in terms of LUT sizes, clocking structure, array layout, and especially interconnect network, which is why this software tool is vendor-specific.

Flex Logix software is called EFLX Compiler and is available for evaluation at no cost to allow customers to see how fast their RTL will run in various process nodes, and what size/area it will take.

EFLX Compiler supports TSMC 16FFC, 16FF+, 28HPC+ and 28HPC for multiple voltage ranges, worst case process corners and -40/0/25/85/125C Tj.

Flex Logix’ EFLX Compiler has a “RUN ALL” button (see the upper left corner of the image below) to allow customers to quickly start getting results: they input their EDIF file and with RUN ALL the EFLX Compiler will a) select an appropriate array size and configuration, b) generate an appropriate I/O pin mapping file, c) generate an appropriate memory (RAMDEF) file, d) then place/route and generate timing based on this.

Then a customer can start to experiment and optimize. The floor planner tool allows the customer to configure arrays using EFLX4K Logic and DSP cores in NxM configurations (see the arrow cursor in the upper right corner: move that left/right/up/down to change the array size as desired). Then each core in the array can be selected as an EFLX4K Logic (“LM”) or EFLX4K DSP (“DSP” = ¾ logic and ¼ MACS, specifically 40 MACs of 22×22 multipliers with pre-adders and accumulators which can be pipelined in strips of 10). The packing/routing/timing can be re-run with varying configurations to see the impact on performance/area.

Another tool for the customer is the placement viewer that can allow a designer to see which blocks of the core are utilized and inspect individual timing paths in several ways: this can give insight in to how to optimize the design for improved performance.

You can also see on the left side column the timing corner selected for viewing is SSGN, 0.72Vj, 125C Tj, RCworst and CCworst. Other timing corners can easily be viewed as well from the drop down menu.

Another tool is the timing analyzer histogram. Again notice the drop down menu providing numerous process corners to choose from. The histogram shows the number of timing paths in each band. It is possible to clock on each column of the histogram to see a list of timing paths, then each timing path can be selected to see how it breaks down step by step from the clock input of a flop, through the logic and interconnect stages to the setup of the destination flop.

These software tools have been in use for many designs at many customers and features are continually being added based on customer requests.

The best way to learn more is to request a demo in person or by web-ex of the software tool processing an example design in real time and to see interactively all the features. Then get an evaluation license to try it on your own design. See for more information and contact information.

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