Author's Latest Posts

The Evolution Of RISC-V Processor Verification: Open Standards And Verification IP

By Imperas - 29 Nov, 2023 - Comments: 0

The OpenHW Group’s [1] Verification task group has been a pioneer in the development of methodologies and verification collateral for RISC-V processor verification. Since 2019 the members have worked together to develop CORE-V-VERIF: a UVM environment for the verification of RISC-V processor cores. Over this period of time the CORE-V-VERIF environment has evolved as new processor verification... » read more

Advanced RISC-V Verification Methodology Projects

By Imperas - 24 May, 2023 - Comments: 0

The open standard of RISC-V offers developers new freedoms to explore new design flexibilities and enable innovations with optimized processors. As a design moves from concept to implementation new resources are appearing to help with standards for testbenches, verification IP reuse, and coverage analysis. RISC-V offers every SoC team the possibility to design an optimized processor, but this a... » read more

RISC-V Processor Verification: Case Study

By Imperas - 22 Sep, 2021 - Comments: 0

Abstract: The open RISC-V instruction set architecture is gaining traction with both semiconductor vendors and systems companies. A key question is how to verify the RISC-V processor implementation, especially when developing the RTL and/or adding custom instructions? This paper reports on the techniques used and lessons learned for the verification of a RV64IMACBNSU RISC-V processor by an exp... » read more

Verilog HDL And Its Ancestors And Descendants

By Imperas - 23 Jun, 2021 - Comments: 0

This paper describes the history of the Verilog hardware description language (HDL), including its influential predecessors and successors. Since its creation in 1984 and first sale in 1985, Verilog has completely revolu- tionized the design of hardware. Verilog enabled the development and wide acceptance of logic synthesis. For large-scale digital logic design, previous schematic-based techniq... » read more

OVP Guide To Using Processor Models

By Imperas - 24 Feb, 2021 - Comments: 0

The OVP simulation technology from Open Virtual Platforms (OVP) and Imperas Software Limited enables very high performance simulation, debug and analysis of virtual platforms containing multiple processor and peripheral models. The OVP technology is extensible, provides the ability to create new models of processors and other platform components by writing C/C++ code that uses application progr... » read more

RISC-V Custom Instruction Flow Application Note

By Imperas - 23 Nov, 2020 - Comments: 0

A RISC-V processor has several defined decode spaces, for example custom0, custom1 etc. into which new custom instructions can be added. OVP Fast processor models can be extended without modification to the pre-compiled and verified base processor model source code using one or more extension libraries. An extension library can be loaded as part of a virtual platform definition in addition to t... » read more