Jeff Wilson

  (all posts)
Jeff Wilson is a DFM product marketing manager in the Calibre organization at Mentor Graphics, a Siemens Company.

Author's Latest Posts

A New Approach To Design-Stage Layout Optimization Can Speed Time To Tapeout While Improving Power Management
By Jeff Wilson - 20 Jul, 2023 - Comments: 0

The right tool for the job makes all the difference. Ever try hammering a nail in with a rock? How many nails did you ruin before you gave up? Or try to tighten a crucial bolt by hand? It takes forever, and you just can’t tighten it enough, so everything’s still kind of wobbly? Yeah, that’s kind of what it’s like trying to use an electronic design automation (EDA) tool to do a job it’... » read more

Creating An Accurate FEOL CMP Model
By Jeff Wilson - 20 Oct, 2016 - Comments: 0

By Ruben Ghulghazaryan, Jeff Wilson, and Ahmed AbouZeid For decades, semiconductor manufacturers have used chemical-mechanical polishing (CMP) as the primary technique for the smoothing and leveling (planarization) of dielectrics and metal layers. CMP modeling allows  design and manufacturing teams to find and fix potential planarization issues before the actual CMP process is applied to a ... » read more

Déjà Vu For CMP Modeling?
By Jeff Wilson - 17 Sep, 2015 - Comments: 0

One definition of design for manufacturing (DFM) is providing knowledge about the impact of the manufacturing process on a design layout to the designers, so they can use that information to improve the robustness, reliability, or yield of their design before tapeout. Essentially, DFM is about designers taking ownership of the full “lifecycle” of a design, and going beyond the required desi... » read more

The Fill Ecosystem Evolves Again
By Jeff Wilson - 23 Jul, 2015 - Comments: 0

Several years ago, we wrote about the ecosystem of fill, and how 20nm technology required a much tighter relationship between the foundry, designers and EDA vendors. While the players remain the same, there have been some interesting shifts in fill techniques and usage as designers move to even-smaller technologies. What continues with each node is the additional complexity of the design flo... » read more

Capacity Constraints And DFM At Mature Nodes
By Jeff Wilson - 19 Mar, 2015 - Comments: 0

We’re witnessing an interesting phenomenon in the SoC segment of the semiconductor industry today. One might call it the “forced waterfall effect.” What I’m referring to is the tendency for production at semiconductor nodes older than the leading edge to be under long-term foundry capacity constraints. Normally this occurs with the “hot process node,” that is, the leading edge wh... » read more

Fill Database Management Strategies At Advanced Nodes
By Jeff Wilson - 13 Nov, 2014 - Comments: 0

Fill has been around for many nodes, and was originally introduced to improve manufacturing results. The foundries learned that by managing density they were able to reduce wafer thickness variations created during chemical-mechanical polishing (CMP) processes, so they introduced density design rule checks (DRC). To meet these density requirements, designers “filled” open areas of the layou... » read more

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