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Jesse Allen

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Jesse Allen is the Knowledge Center administrator and a senior editor at Semiconductor Engineering.

Author's Latest Posts

Blog Review: Oct. 5
By Jesse Allen - 05 Oct, 2016 - Comments: 0

Mentor's Michael White explores why established nodes are experiencing such an unexpectedly long lifespan and how that is driving new challenges for designers. Cadence's Ann Keffer checks out the history of Ethernet and how it won the battle to become the dominant network protocol. Is your IoT device fueling a botnet? Vulnerable firmware on internet connected devices was behind one of the... » read more

Power/Performance Bits: Oct. 4
By Jesse Allen - 04 Oct, 2016 - Comments: 0

Solar battery Chemists at the University of Wisconsin–Madison and the King Abdullah University of Science and Technology in Saudi Arabia integrated solar cells with a large-capacity battery in a single device that eliminates the usual intermediate step of making electricity and, instead, transfers the energy directly to the battery's electrolyte. The team used a redox flow battery, or R... » read more

The Week In Review: Design
By Jesse Allen - 30 Sep, 2016 - Comments: 0

Numbers EDA and IP sales increased 5.6% in Q2 to $2.013 billion, up from $1.907 billion in the same period in 2015, according to the most recent Electronic System Design Alliance numbers. Asia/Pacific revenue increased 10.9% to $608.1 million; Japan increased 15.7% to $211.4 million. The Americas increased 4.4% to $908.4 million. IP Cadence launched the latest generation of its Xtensa ... » read more

Blog Review: Sept. 28
By Jesse Allen - 28 Sep, 2016 - Comments: 0

Cadence's Paul McLellan provides a glimpse of TSMC's roadmap, including what to look for at 7nm, low-power processes, and the ecosystem around the process. Mentor's Stephen Pateras notes that throughout the evolution of DFT, two rules for success have persisted. Early analysis suggests the largest DDoS attack in history, targeted at security reporter Brian Krebs, may have leveraged flaws ... » read more

Power/Performance Bits: Sept. 27
By Jesse Allen - 27 Sep, 2016 - Comments: 0

Self-organizing circuits Researchers studying the behavior of nanoscale materials at the Department of Energy's Oak Ridge National Laboratory discovered that due an unusual feature of certain complex oxides called phase separation, individual nanoscale regions can behave as self-organized circuit elements, which could support new multifunctional types of computing architectures. "Within a... » read more

The Week In Review: Design
By Jesse Allen - 23 Sep, 2016 - Comments: 0

Tools Real Intent updated its Ascent Lint product, adding 50 new customer-driven rules, improved support of VHDL and System Verilog, and a new database-driven debugger with an integrated source browser and improved schematic visualization. IP ARM launched a new real-time processor with advanced safety features for autonomous vehicles and medical and industrial robots. The processor, Co... » read more

Blog Review: Sept. 21
By Jesse Allen - 21 Sep, 2016 - Comments: 0

Mentor's Ricardo Anguiano takes a look at a proposal to prevent auto accidents from becoming pile-ups: the relaying of hazard information to the cloud and on to upcoming vehicles. Why get rid of 3.5mm audio jacks? Synopsys' Michael Posner says it's all about the power optimization in the upcoming USB Type-C digital audio specification. NXP's Anand Kannan also thinks Type-C should be the d... » read more

Power/Performance Bits: Sept. 20
By Jesse Allen - 20 Sep, 2016 - Comments: 0

Energy-harvesting fabric Researchers at the Georgia Institute of Technology and Chongqing University in China developed a fabric that can simultaneously harvest energy from both sunshine and motion. The fabric, just .32mm thick, was constructed using a commercial textile machine to weave together solar cells constructed from lightweight polymer fibers with fiber-based triboelectric nanoge... » read more

The Week In Review: Design
By Jesse Allen - 16 Sep, 2016 - Comments: 0

IP Sonics unveiled Energy Processing Unit (EPU) IP, based on the company's ICE-Grain power architecture, to better manage and control circuit idle time. The IP facilitates design of SoC power architecture and implementation and verification of the resulting power management subsystem. Synopsys debuted ARC SEM security processors with timing and power randomization features to protect agai... » read more

Blog Review: Sept. 14
By Jesse Allen - 14 Sep, 2016 - Comments: 0

Are wide bandgap lll-V power devices feasible? Applied's Ben Lee considers the challenges, and potential rewards, of silicon carbide and gallium nitride. DVCon India chair Gaurav Jalan chats with keynote speaker Alok Jain about the challenges of verifying complex SoCs, the unique verification needs of the IoT, and what might lie beyond UVM. From power intent abstraction to automatic power... » read more

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