The Week In Review: Design

ARM’s safety-focused processor; evaluating memory IP; lint product update; cache memory controller; TSMC process support.



Real Intent updated its Ascent Lint product, adding 50 new customer-driven rules, improved support of VHDL and System Verilog, and a new database-driven debugger with an integrated source browser and improved schematic visualization.


ARM launched a new real-time processor with advanced safety features for autonomous vehicles and medical and industrial robots. The processor, Cortex-R52, offers hardware-enforced separation of software tasks to ensure safety-critical code is fully isolated, allowing the hardware to be managed by a software hypervisor policing the execution and resourcing of tasks. Cadence announced an adoption kit for the processor, and Synopsys reports broad tool support for the new architecture.

eSilicon expanded its STAR Navigator to include automated, online quoting and purchasing capabilities for memory IP and I/O libraries, with matching to assist in PPA evaluation.  According to the company, “designers can download front-end views, run simulations in their own environments and then purchase the back-end views of the IP and I/Os that best fit their design.”

CAST and Silesia Devices rolled out a new cache memory controller IP core for the addition of single or multilevel cache memory to systems using cache-less 32-bit processors such as the BA20 PipeLineZero or ARM Cortex-M0 processors.

TSMC Updates

Cadence presented a broad portfolio of interface and memory IP for automotive applications supporting TSMC’s 16nm FinFET Compact (16FFC) process. Cadence anticipates initial customer deliveries of the first high-speed SerDes and low-latency DDR IP for TSMC’s 16FFC process in the fourth quarter of this year.

Cadence also released a flow for TSMC’s advanced wafer-level Integrated Fan-Out (InFO) packaging technology.

Mentor Graphics’ Analog FastSPICE and multiple Calibre products were certified for TSMC 16FFC FinFET V1.0 and the latest DRM and SPICE version of 7nm FinFET process technologies.

Synopsys announced successful tapeout of multiple customer test chips with DesignWare logic libraries and embedded memories on TSMC’s 7nm FinFET process. Interface IP in development for the process includes USB, PCI Express, DDR, MIPI, DisplayPort, SATA and Ethernet.

Plus, Synopsys reports its Foundation IP, including logic libraries and embedded memories, meets automotive AEC-Q100 Grade 1 temperature requirements (-40C to +150C junction) on the TSMC 16FFC and 28nm High-Performance Compact+ (28HPC+) processes. TSMC also certified a suite of the company’s digital, custom and signoff tools for the 16FFC process.

And ANSYS is collaborating with TSMC on a suite of solutions for fan-out technology, including multi-die analysis for extraction, power, reliability, signal and power integrity, and thermal and electromagnetic interference.


Toshiba licensed Arteris’ FlexNoC interconnect IP and the companion FlexNoC Resilience Package for use in its image recognition processors for ADAS applications. Toshiba cited ability to optimally manage the high bandwidth and low latency quality of service requirements and error-correcting code (ECC) protection of on-chip communications and hardware duplication of interconnect components.

Mentor Graphics’ emulation platform was used by Starblaze Technology for a specialized high-speed, enterprise-based SSD storage design. Starbaze cited virtualization technology and memory protocol support, and rich software debug capabilities.

Related Stories
The Week In Review: Design (9/16/16)
Energy processing IP; security processors; FPGA library reuse; MPEG-H and Dolby AC-4 decoders; simulation software for startups.
The Week In Review: Design (9/9/16)
Intel acquires Movidius and spins out McAfee; EDA market set to grow; IDE for Synopsys VDKs; modeling parasitic effects.

Leave a Reply

(Note: This name will be displayed publicly)