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Jesse Allen

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Jesse Allen is the Knowledge Center administrator and a senior editor at Semiconductor Engineering.

Author's Latest Posts

Blog Review: Nov. 3
By Jesse Allen - 03 Nov, 2021 - Comments: 0

In a blog for Arm, Matthew Griffin of the 311 Institute warns that cybersecurity is an increasingly pressing problem, with large criminal organizations raking in large sums of money and attacks able to impact a wide range of physical systems. Cadence's Paul McLellan checks out Google's video encoder chip and how it helps lower the CPU recycles required by the vast number of videos uploaded t... » read more

Power/Performance Bits: Nov. 2
By Jesse Allen - 02 Nov, 2021 - Comments: 0

GaN CMOS ICs Researchers from the Hong Kong University of Science and Technology (HKUST) are working to increase the functionality available to wide bandgap gallium nitride (GaN) electronics. GaN is frequently used in power electronics, such as power converters and supplies. However, GaN CMOS technology has been hampered by the difficulties in implementing p-channel transistors and integrat... » read more

Week In Review: Design, Low Power
By Jesse Allen - 29 Oct, 2021 - Comments: 0

Arteris IP uncorked its initial public offering this week, a rare occurrence for a semiconductor IP vendor over the past couple decades. The stock began trading on the Nasdaq Global Market on Wednesday under the ticker symbol AIP, gaining more than 40% on its first day. Tools Codasip updated its Studio processor design toolset. Version 9.1 includes an expanded bus support with full AXI for ... » read more

Blog Review: Oct. 27
By Jesse Allen - 27 Oct, 2021 - Comments: 0

Siemens EDA's Ray Salemi continues looking into using Python for verification by looking at how pyuvm simplifies and refactors the UVM TLM system to take advantage of the fact that Python has multiple inheritance and no typing. Cadence's Paul McLellan listens in as Larry Disenhof explains the impact that export regulations have on EDA tools and IP products and changes in a rapidly shifting l... » read more

Power/Performance Bits: Oct. 26
By Jesse Allen - 26 Oct, 2021 - Comments: 0

Printing circuits on irregular shapes Researchers at Pennsylvania State University propose a way to print biodegradable circuits on irregular, complex shapes. “We are trying to enable direct fabrication of circuits on freeform, 3-D geometries,” said Huanyu “Larry” Cheng, professor in Penn State's Department of Engineering Science and Mechanics (ESM). “Printing on complicated objec... » read more

Week In Review: Design, Low Power
By Jesse Allen - 22 Oct, 2021 - Comments: 0

Tools Cadence's digital and custom/analog flows were certified for TSMC's N3 and N4 process technologies. Updates for the digital flow includes efficient processing of large libraries, additional accuracy during library cell characterization and static timing analysis, and support for accurate leakage calculation required in N3 and static power calculation for new N3 cells. Synopsys' digita... » read more

Blog Review: Oct. 20
By Jesse Allen - 20 Oct, 2021 - Comments: 0

Siemens EDA's Sumit Vishwakarma promotes ironing out preliminary bugs by using a real number model to describe an analog block as a discrete floating-point model and enable it to simulate in a digital solver at near-digital simulation speeds. Synopsys' Taylor Armerding explains how including security in the software development process from the beginning planning stages onward will help IoT ... » read more

Power/Performance Bits: Oct. 19
By Jesse Allen - 19 Oct, 2021 - Comments: 0

Post-quantum crypto chip Researchers at the Technical University of Munich (TUM) designed and had fabricated an ASIC to run new encryption algorithms that can stand up to quantum computing. “Ours is the first chip for post-quantum cryptography to be based entirely on a hardware/software co-design approach,” said Georg Sigl, Professor of Security in Information Technology at TUM. “As a... » read more

Week In Review: Design, Low Power
By Jesse Allen - 15 Oct, 2021 - Comments: 0

Nvidia acquired Oski Technology. Oski provides formal verification methodologies and consulting services, and Nvidia said that the acquisition will allow it to increase its investment in formal verification strategies. Oski's Gurugram, India, design center will become Nvidia's fourth engineering office in the country. Based in San Jose, Calif., it was founded in 2005. Terms of the deal were not... » read more

Blog Review: Oct. 13
By Jesse Allen - 13 Oct, 2021 - Comments: 0

Cadence's Paul McLellan checks out what Google learned in developing multiple generations of its TPU processor, including unequal advancement of logic and memory, the importance of compiler of compatibility, and designing for total cost of ownership. Siemens EDA's Jake Wiltgen argues for the importance of linting as part of eliminating systematic failures in designs complying with ISO 26262.... » read more

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