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Jesse Allen

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Jesse Allen is the Knowledge Center administrator and a senior editor at Semiconductor Engineering.

Author's Latest Posts

Week In Review: Design, Low Power
By Jesse Allen - 22 Oct, 2021 - Comments: 0

Tools Cadence's digital and custom/analog flows were certified for TSMC's N3 and N4 process technologies. Updates for the digital flow includes efficient processing of large libraries, additional accuracy during library cell characterization and static timing analysis, and support for accurate leakage calculation required in N3 and static power calculation for new N3 cells. Synopsys' digita... » read more

Blog Review: Oct. 20
By Jesse Allen - 20 Oct, 2021 - Comments: 0

Siemens EDA's Sumit Vishwakarma promotes ironing out preliminary bugs by using a real number model to describe an analog block as a discrete floating-point model and enable it to simulate in a digital solver at near-digital simulation speeds. Synopsys' Taylor Armerding explains how including security in the software development process from the beginning planning stages onward will help IoT ... » read more

Power/Performance Bits: Oct. 19
By Jesse Allen - 19 Oct, 2021 - Comments: 0

Post-quantum crypto chip Researchers at the Technical University of Munich (TUM) designed and had fabricated an ASIC to run new encryption algorithms that can stand up to quantum computing. “Ours is the first chip for post-quantum cryptography to be based entirely on a hardware/software co-design approach,” said Georg Sigl, Professor of Security in Information Technology at TUM. “As a... » read more

Week In Review: Design, Low Power
By Jesse Allen - 15 Oct, 2021 - Comments: 0

Nvidia acquired Oski Technology. Oski provides formal verification methodologies and consulting services, and Nvidia said that the acquisition will allow it to increase its investment in formal verification strategies. Oski's Gurugram, India, design center will become Nvidia's fourth engineering office in the country. Based in San Jose, Calif., it was founded in 2005. Terms of the deal were not... » read more

Blog Review: Oct. 13
By Jesse Allen - 13 Oct, 2021 - Comments: 0

Cadence's Paul McLellan checks out what Google learned in developing multiple generations of its TPU processor, including unequal advancement of logic and memory, the importance of compiler of compatibility, and designing for total cost of ownership. Siemens EDA's Jake Wiltgen argues for the importance of linting as part of eliminating systematic failures in designs complying with ISO 26262.... » read more

Power/Performance Bits: Oct. 11
By Jesse Allen - 11 Oct, 2021 - Comments: 0

Finer printed circuits Researchers from the National Institute for Materials Science in Japan, Jiangnan University, Zhengzhou University, Senju Metal Industry Co., and C-INK Co. developed a way to print smaller features for printed electronics. The directed self-assembly method increases the chemical polarity of predetermined areas on a surface, which promoted selective adhesion of metallic na... » read more

Week In Review: Design, Low Power
By Jesse Allen - 08 Oct, 2021 - Comments: 0

Arteris IP plans to become a public company. It filed a registration statement with the SEC for an IPO, and intends to list on Nasdaq. The number of shares to be offered and the price range for the proposed offering have not yet been determined. Arteris IP provides network-on-chip interconnect IP, cache coherent interconnects, and packages to speed functional safety certification alongside IP d... » read more

Blog Review: Oct. 6
By Jesse Allen - 06 Oct, 2021 - Comments: 0

Arizona State University's Jae-sun Seo and Arm's Paul Whatmough introduce a fully-parallel and fully-pipelined FPGA accelerator for sparse CNNs that can eliminate off-chip memory access and also efficiently support elementwise pruning of CNN weights. Cadence's Paul McLellan highlights trends seen at the recent Hot Chips, from machine learning and advanced packaging driving higher performance... » read more

Power/Performance Bits: Oct. 5
By Jesse Allen - 05 Oct, 2021 - Comments: 0

Modeling resistive-switching memory Researchers from Singapore University of Technology and Design (SUTD) and Chang Gung University developed a new toolkit for modeling current in resistive-switching memory devices. The team said that traditional physical-based models need to consider complex behaviors to model current in resistive memory, and there's a risk of permanent device damage due t... » read more

Startup Funding: September 2021
By Jesse Allen - 04 Oct, 2021 - Comments: 0

Startups focused on data center chips had a big month in September. A new emergent from stealth promises to accelerate big data analytics, and startups proving CXL connectivity and high-performance RISC-V chiplets also drew funding. On the other end of the spectrum, NB-IoT and edge AI designers saw investment while a company providing on-chip monitoring can predict when chips will fail. Plus, c... » read more

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