Blog Review: Oct. 6

FPGA accelerator for CNNs; design trends; challenges of AI chips; formal equation.


Arizona State University’s Jae-sun Seo and Arm’s Paul Whatmough introduce a fully-parallel and fully-pipelined FPGA accelerator for sparse CNNs that can eliminate off-chip memory access and also efficiently support elementwise pruning of CNN weights.

Cadence’s Paul McLellan highlights trends seen at the recent Hot Chips, from machine learning and advanced packaging driving higher performance systems to increased attention on the unequal improvement of logic and memory.

Synopsys’ Kiran Vittal looks into how the recent boom of AI chips has changed the silicon engineering landscape, key verification challenges and opportunities to expand the use of AI chips across applications, and why hardware security will be vital going forward.

Siemens EDA’s Joe Hupcey III explains how formal verification can be exhaustive using a simple equation, without a complicated academic proof.

In a blog for Ansys, Trent Martin of Intuitive Machines explains how multiphysics simulation is helping land unmanned vehicles on the Moon in 2022.

In a blog for SEMI, KX’s Bill Pierson argues that the semiconductor industry needs to optimize existing factories in order to increase productivity and yield by implementing smart manufacturing solutions and utilizing data generated.

Onsemi’s Marc Bracken checks out how on board chargers in plug-in electric vehicles work and why big differences in EV battery capacity is driving a need for scalability and flexibility in OBC design.

Nvidia’s Debraj Sinha finds that edge computing can provide significant benefits to manufacturing, enabling sensor-enabled devices to collect and process data locally for real-time AI with minimal latency.

For a break from reading, check out some of the latest videos:

Where Open Cavity Plastic Packaging can help deal with obsolescence through retrofitting.

What goes wrong when Optimizing AI Systems and what to do about it.

Low-Power Always-On Circuits raise the question of what happens when things never shut down.

Why Using ML In EDA is becoming a requirement for designing complex chips.

What’s Changing In DRAM and the impact of shrinking features on memory.

What’s available, what’s missing, what’s next for Working With RISC-V.

Changes In Auto Architectures as cars move from driver-centric to driverless functionality.

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