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Blog Review: Oct. 20

Debug with real number models; early security; floating point; side-channel attacks.

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Siemens EDA’s Sumit Vishwakarma promotes ironing out preliminary bugs by using a real number model to describe an analog block as a discrete floating-point model and enable it to simulate in a digital solver at near-digital simulation speeds.

Synopsys’ Taylor Armerding explains how including security in the software development process from the beginning planning stages onward will help IoT and other connected devices be more resilient to cyberattacks.

Cadence’s Paul McLellan considers floating point numbers, why they’re used, and some of the unexpected behaviors they exhibit.

A Rambus writer explains how side-channel attacks work and details some of the most common attack methodologies, with a particular focus on differential power analysis attacks and the countermeasures available.

Ansys’ Jamie Gooch points to the importance of optics and simulating how light behaves at the nanophotonic level and how it is manipulated with instruments and lenses for the design of cameras for consumer and ADAS applications.

Arm’s Reinhard Keil argues for adopting cloud-based and hybrid embedded development tools that provide continuous integration flows, model optimization for machine learning, and device provisioning for deployment.

ESD Alliance’s Bob Smith chats with Nikos Zervas of CAST about the early days of the silicon IP market, when it started to take off, and what’s changed in the market since.

Western Digital’s Ronni Shendar checks out the boom in smallsats, small satellites under 1,000 pounds that can be constructed much more easily than their larger counterparts, and how they are using off-the-shelf components with software mechanisms to provide resiliency instead of traditional radiation-hardened silicon.

Plus, don’t miss the blogs featured in the latest Low Power-High Performance newsletter:

Synopsys’ Moninder Singh explains why the complexity of interface IP makes it difficult to keep transistor netlist views logically equivalent to reference Verilog models.

Arm’s Remy Pottier contends that creating an ecosystem for pervasive computing systems will require extensive trial and error.

Fraunhofer’s Roland Jancke warns that special attention must be paid to the non-functional properties of RF components.

Ansys’ Tyler Ferris identifies three places where electronics typically go bad on a PCB.

Infineon’s Olaf Bendix lays out steps to identify a suitable gate driver IC based on the peak current and power dissipation requirements of an application.

Rambus’ Paul Karazuba shows how to minimize performance overhead while protecting high-value data passed across interconnects.

Cadence’s Shyam Sharma zeroes in on requirements to watch out for when combining multiple individual DRAMs to create higher-density memories.

Siemens’ Joe Davis highlights problems in analyzing power for large analog designs.

Synopsys’ Anika Malhotra looks at using the IP-XACT integration standard to speed time to market and reduce costs.



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