Bringing Scalable Power Integrity Analysis To Analog IC Designs

Power integrity is a broad term in integrated circuit (IC) design and verification. However, when IC engineers are working through design signoff, power integrity analysis focuses on three specific aspects of a design:

• Power: Verify the chip design as implemented provides the total predicted power under different operating modes.
• Performance: Find and eliminate performance issues affected by layout, such as at-speed fall-out, functional failures, etc.
• Reliability: Find and eliminate layout implementation issues that may impair performance and product life, such as electromigration (EM), self-heating, etc.

To successfully satisfy the growing demand for products that incorporate sensor systems, analog design companies must ensure that their system-on-chips (SoCs) can provide the power integrity and operational reliability that the consumer expects and demands. Power integrity analysis enables design teams to ensure that the implementation of a chip meets the power design targets from the original specification. In turn, that provides assurance that the chip will achieve both the technical and business goals of the project.

Challenges in analog power analysis

However, exponential growth in analog and sensor components, as well as the need for functional integration of digital and analog components, are stressing the power integrity verification process (figure 1). Analog IC designers simply don’t have the electronic design automation (EDA) power analysis tools and methodologies they need when they get to the confluence of physical and electrical signoff.

Fig. 1: The number of analog blocks is growing at 10-15% CAGR across technology nodes from 5nm to 28nm. The number of power domains is also growing across all technologies, with the most advanced technologies growing the fastest. (Source: Semico [1])

Design abstraction is perfectly suitable for digital flows, and existing EM/IR signoff tools provide good scalability and performance for digital designs, but analog design flows don’t lend themselves to such compartmentalized processes. Analog designers want to run SPICE-based dynamic analysis to ensure they capture all the effects in a chip in real operating modes. Existing EDA tools can do this for small analog designs, but as a company starts incorporating memories and large sensor arrays into designs and puts more of these designs together into analog systems, the capacity and performance of SPICE simulators create a constraint beyond which they can’t simulate the whole circuit. Simulation-based dynamic analysis is generally limited to designs with fewer than ~1-2M transistors. Beyond this size, the typical approach is static analysis, or SPICE simulation of hand-selected nets and portions of the chip. Design teams get their chips out the door, but it’s costing their companies engineering time and coverage, both of which not only increase the cost of the design, but also the risk to the final product quality and the schedule.

In addition, both digital and analog power analysis tools are notably problematic to use, especially for design teams that only perform power integrity analysis a few times each year. Collecting the required inputs is almost always difficult and time-consuming, and designers must create additional setups from the base process design kit (PDK).

What does all that mean? For digital designs, not that much. Design companies use the available tools to get the job done, even if it’s not always the most expedient process. For analog designs, though, the largest, most complex systems end up being over-designed and/or analyzed with tedious engineering workarounds that incur engineer time and both product and schedule risk. And that means more time, more resources, and higher costs. Analog and mixed-signal chip designers need a fast, effective, accurate means of scaling their power analysis to the full analog system level, then to the combined digital/analog chip, and finally to multi-chip designs. However, the EDA industry simply hasn’t had a scalable analog power analysis signoff solution. Until now.

Scalable analog power analysis

The mPower toolsuite from Siemens EDA enables companies to perform signoff EM/IR analysis of both analog and digital circuits to ensure that the as-implemented design will meet performance and reliability targets when manufactured.

While it can handle the largest digital designs on the market, mPower has the ability to analyze analog and sensor systems of all sizes, enabling design teams to achieve high-confidence signoff results for even the biggest full-chip designs. Of course, that scalability requires a foundation. At the core of the solution is a comprehensive set of engines individually optimized for the data on which they operate and designed to work efficiently on the types of heterogeneous compute grids that companies commonly use.

For analog designers, the mPower Analog high-capacity (HC) dynamic analysis functionality provides full coverage of simulation-based signoff for analog circuits of any size (figure 2). HC dynamic analysis provides full-chip and array analyses from block-level SPICE simulations for detailed power analysis and faster overall turnaround times. It also enables faster iterations early in the design cycle by using pre-layout SPICE simulations.

Fig. 2: HC dynamic analysis replaces the mix of dynamic and static analysis with simulation-based EM/IR analysis for the largest, most complex analog blocks and chips.

But there’s another important aspect to EDA tools—ease of use. It doesn’t matter if a tool’s core functionality is great if designers can’t use it easily and effectively. Except for the very largest companies, EM/IR sign-off is a job that most design engineers do once or twice a year. This means that every engineer, to some extent, starts over every time. While CAD teams at the big companies can and do build wrappers around EDA tools to make them easier for their design teams to use, this approach (surprise!) just isn’t practical for the majority of design companies. Those designers end up spending a lot of their time just remembering how to run the tool or figuring out what the results mean.

To ensure ease of use is a core constituent of the tool, mPower Analog uses industry-standard formats and the simple and familiar TCL command language. In addition, the mPower Analog tool works with all parasitic extractors and simulators. A fast, stable, and easy-to-use quad-view GUI for invocation and results debugging makes it simple for designers to identify root cause, then highlight results into design tools through the Calibre RVE interface for fixing (figure 3).

Fig. 3: Engineers can quickly and easily run a power integrity analysis, then debug the results using the mPower GUI.

Summary

Performance is always a key metric for EDA tools, but the biggest performance metric is when an EDA tool enables you to do something that you just couldn’t do before at all. With accurate, easy-to-use, scalable power integrity verification that can be readily integrated into existing analog and digital design and verification flows, design teams can now employ a qualified EDA power analysis tool to accurately measure the IR drop and EM performance of their large analog systems without having to invest weeks of engineering time or worry about under-analyzing their designs.

References
[1]  Semico Research & Consulting Group, 2019. “ASIC Design Starts for 2019 by Key End Market Applications.” https://semico.com/content/asic-design-starts-2019-key-end-market-applications

Additional information
Introducing mPower: Uncompromised power integrity for the whole design, at any scale