Choosing A Gate Driver For Silicon Carbide MOSFETs

Steps to identify a suitable gate driver IC based on the peak current and power dissipation requirements of an application.


If you are going to use a silicon carbide (SiC) MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) in your next development, you will ask yourself: how do I develop the best gate driver for it?

The answer to this question is: identify a suitable gate driver IC based on the peak current and power dissipation requirements of your application and a fitting gate resistor for your SiC MOSFET. At the end, fine tune your design in your laboratory.

Doing this, keep in mind that the gate driver IC you select needs to accommodate the high switching speeds of SiC MOSFETs, as they can reach a slew rate of 50 kV/µs or more and can switch faster than 100 kHz. And the reverse recovery charge Qrr of their freewheeling intrinsic body diode is quite low. You will also have to choose the best value for the gate resistor and the right part to assure a proper operation of your design.

This blog will outline the steps necessary to achieve these goals.

Gate driver design step-by-step

When designing a gate driver, you have two choices: to use an integrated gate driver IC or a discrete solution. Using integrated parts like our EiceDRIVER gate driver ICs has many advantages: the design is less complex, the development time shorter, the bill of materials smaller, and the board space reduced. And finally, they improve the reliability as well.

The selection of a gate driver IC and its gate resistor is usually an iterative process: You start with first assumptions and fine tune your design during the process. If you find that one of the parts does not satisfy your requirements, you start over with new values.

Step 1: Determine the peak current and select the gate driver

Your first step is to determine the peak current Ig based on values in the datasheet of the SiC device. While the numbers there result from a highly optimized reference design and your application might have different operation conditions, they are a good starting point for the calculation of the gate current.

Begin with the following equation:

with ∆VGS,datasheet being the difference between the on-state and the off-state gate voltages of the SiC MOSFET according to the datasheet:

Please keep in mind that this equation ignores the internal resistance of the gate driver; we simply do not know it yet.

There are two sections in the datasheet of the SiC device, which are relevant for the calculation: the switching characteristics, giving you the values for RG,ext and the on- and off-state voltages, and the static characteristics, which give you the value for the internal gate resistor RG,int.

Having all data, you can now compute the peak current. The result will be the reference value for the selection of the gate driver. Compare it to the high- and low-level output peak currents IOUT+,PEAK and IOUT-,PEAK values in the driver’s datasheet. Also, check the gate voltage swing noted under test conditions if it matches the requirements of your application.

Step 2: Select the gate resistor value

Now, calculate the value of RG,ext for the gate resistor based on your application’s gate voltage swing. The goal here is to get the same or a similar switching performance of the SiC MOSFET as given in its datasheet. Please note that there is no general formula for computing the value of the resistance, but the following ones will help you to reach your goal. As the value for RG,ext depends on the application, we will use RG,application from now on.

Here, the value of ∆VGS,application depends on the application and the power switch.

The switching behavior is determined by the combination of the gate resistor and the input capacitance (CISS) of the power switch. Since CISS is nonlinear, it is easier to calculate with the total gate charge QG and the switching times. You will find the values for the rise time tr and the turn-on delay time td(on) in the data sheet of the MOSFET.

You can extract the value of the gate charge QG for your application from the gate charge diagram in the datasheet of the SiC device. Select the points for the voltages VVEE2 and VVCC2 and read the values for the off- and on-state gate charges. Then calculate QG as difference between these two charges. If the diagram does not represent your used voltage swing, extrapolate the curve linearly.

Now calculate the value for RG,application and use the result for your next steps.

Step 3: Calculate the expected power dissipation

Now, for the calculation of the power dissipation PD of the gate driver IC and the external gate resistor, we use a simplified formula. It assumes that the power losses during switching are only dissipated in the output stage of the gate driver IC and are dominated by the charging and discharging of the gate capacitance.

This way, you can regard the power dissipated as a function of the gate charge in the application, the switching frequency, and the voltage swing of the gate driver output.

The reality is slightly different, as the gate resistances also take over some of the losses. But this means that your calculation will be on the safe side.

Once you have computed the power dissipated, compare your result to the value in the datasheet for the maximum power dissipation PD,OUT in the output side of the driver at 25°C. It should be smaller or equal to this value.

As the power dissipation leads to a temperature increase at the IC’s junction, you also have to consider the linear derating between the PD,OUT test condition and the maximum junction temperature using the formula below:

You can find the value for the thermal resistance between the junction and the ambient Rth(j-a) in the datasheet of the SiC MOSFET.

You might see a difference between a measured temperature and the calculated one. This happens if the copper area for cooling in your application is smaller than the one in the reference design used to obtain the datasheet values.

Step 4: Validate the calculations in your laboratory

In this step, you will verify that SiC devices, gate driver ICs and gate resistors work in your application as expected, and you will do that through lab-measurements. These measurements will either prove that the assumptions and calculations you made result in a safe switching behavior of the SiC MOSFET, or not. If not, repeat the steps 1 through 4 with another value of the gate resistor RG.

For the validation of your design, we recommend three tests:

In the first one, you will verify the absence of parasitic turn-on events triggered by the dv/dt transients under worst-case conditions. For this, run the test under the lowest application temperature, the lowest drain current, and the worst-case gate-source voltage.

Start with looking for oscillations in the gate voltage and source currents using your oscilloscope. These oscillations are not desired and should be kept under control. Transients showing there can lead to an unwanted turn-on of the SiC device, as the off-state gate voltage can become higher than the gate threshold voltage (VGS(th)) due to parasitic capacitances. These turn-on events will degrade the SiC device early, so they should never occur. The best measurement method for this is a double-pulse test.

If there are oscillations, change the value of the gate resistor to eliminate them. If you increase the gate resistor value, the slew rate of dv/dt will be reduced, as the transistor speeds will slow down. A smaller gate resistor value will lead to a faster switching of the SiC device and therefore higher dv/dt transients are generated. Every time you change the value for the gate resistor, redo the measurement.

Table 1: Main physical effects on the application by the values for the gate resistor RG.

Table 1 explains how changing the value for the gate resistor will influence other parameters as well.

Once you did this test, the gate driver is adjusted, and you can be sure that no parasitic turn-on events occur.

The second test is to measure the temperature of the gate driver IC during steady state operation, ideally under the expected operating ambient temperatures. Your goal here is to prove that the power losses in the gate driver are not higher than expected and that the junction temperature is kept within the absolute limits stated in the datasheet. Use an infrared camera for this test, but thermocouples can be useful as well.

In addition, use the equation below to determine the junction temperature numerically:

You can get the value of the thermal coefficient for junction to top of package Ψth,jt from the driver’s datasheet. If you measure at room temperature, add the resulting temperature difference to the applications worst-case temperature.

The thermal load of the gate resistor is often mistakenly neglected, but it is important. So, during the third test you will validate the loading of the gate resistor. Measure the heating of the resistor during a thermal steady-state operation with an IR-camera and compare it to the datasheet.

You should also calculate the peak power of the resistor and check it against its single-pulse rating as given in its datasheet. For this, use the following formula:

The resulting PRg,Pk should not be higher than the maximum datasheet rating.

As soon as this final value is confirmed, the selected gate driver IC and the gate resistor chosen can be used for your application. Our EiceDRIVER gate driver ICs will further help you to create fast and secure gate-drive designs for SIC-MOSFETs.

Watch this training video for the step-by-step explanation: Gate driver design cookbook for SiC MOSFETs and SiC MOSFET modules.

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