Using IP-XACT To Solve Design And Verification Problems

Using the IP integration standard to speed time to market and reduce costs.


As today’s SoC designs grow more complex and time-to-market (TTM) pressures rise, designers are looking for techniques to build and update designs easily. Key elements for addressing these SoC challenges include the incorporation of more commercial IP components, internal design IP reuse, and extensive automation of design and verification activities. Enhanced interoperability and reusability of IP allow companies to share the costs and risks of hardware development, thereby avoiding duplication of development efforts.

The wide availability of I/O controllers, processors, bus interfaces, network on chip (NoC) infrastructure and other types of IP has been a great benefit for SoC teams. However, using someone else’s design is not without its own challenges. Designers must understand different IP behavior and integrate all the blocks into the chip either manually or through some form of automation. To achieve real productivity, it is essential to overcome the tiresome effort of ad hoc IP integration. A common platform or language to describe IP is essential, and the IEEE 1685 standard (IP-XACT) was created specifically to fill this need. IP-XACT provides ease of system integration, verification, and automation to accelerate TTM.

Background on IP-XACT
IEEE 1685 is titled “IEEE Standard for IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tool Flows.” IP-XACT was originally developed by the SPIRIT Consortium, which merged into the Accellera Systems Initiative. It was standardized by the IEEE, with the latest revision released in 2014, and this version was adopted as IEC 62014-4:2015. IP-XACT was developed to enable IP vendors to provide a single description of their components to all their customers, regardless of the design language or tools that they use, and to enable developers to transfer designs between environments that use different design languages.

IP-XACT describes the meta-data of IP designs and flows, and the interconnection of IP interfaces, in a standard specification plus XML schema files that define the syntax of the standard. For each IP component, the XML description provides a wide range of information that may include:

  • Vendor, library, name and version
  • File set and path to files
  • Bus interfaces, signal maps, RTL models and parameters
  • Fabric channels and bridges
  • Memory maps, address blocks and memory-mapped registers

How IP-XACT Fits into the Design Flow
IP-XACT plays a key role in automating many aspects of SoC assembly, integrating both commercial IP and reused internal designs. It is extremely flexible; it works on projects that have no legacy IP and simply need a mechanism to allow different design teams to work on subsystems with easy integration into target SoC devices. There are commercial core tools available to guide designers through the assembly and configuration of an IP-based subsystem, creating and packaging the complete subsystem for reuse at the SoC level. Synopsys and some other IP vendors provide IP-XACT descriptions to enable this flow.

IP-XACT also helps in the transition from design to verification. In the traditional development flow, there is no solid relation between the design process and the verification process. This wastes a lot of time and may delay reaching verification closure. IP-XACT solves this problem by streamlining the flow and providing a common reference for all development teams. Most of the design information can be reused while bringing up the verification environment.

How IP-XACT Fits into the Verification Flow
One typical verification challenge in developing testbenches is having the expertise/knowledge of the IP. Use of multiple IP suppliers results in inconsistent verification views. When reusing IP, identifying the right testcases for integration verification is a tedious task. In a complex SoC where IPs from multiple vendors are used, there is a high probability of integration errors. The impact of changes in specification are problematic and error prone. By following the IP-XACT format, integration and design information of third-party IP is clean and consistent, helping design and verification engineers to perform error-free integration and set up their verification environments correctly.

The standardization of IP-XACT helps solve these challenges through representation of design topology and register address mapping. There is a single source for all representations, portable across multiple tools and vendors. IP-XACT is flexible, quickly adaptable to any change in a design under development and reusable across different design teams and different projects. Further, with an IP-XACT file available, designers can use automated testbench generation tools to help shorten the testbench bring-up time, run system-level tests and generate a testbench that is scalable from IP to SoC. The “time-to-first-test” metric, often on the order of days to weeks depending on design complexity, is reduced to less than an hour.


The Synopsys automated IP-XACT-based SoC solutions simplify specification integration, design and documentation for the semiconductor industry to successfully tape out designs faster at less cost. This shortens TTM and greatly reduces the chances for integration-related design bugs.

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