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Jesse Allen

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Jesse Allen is the Knowledge Center administrator and a senior editor at Semiconductor Engineering.

Author's Latest Posts

Power/Performance Bits: Sept. 15
By Jesse Allen - 15 Sep, 2020 - Comments: 0

Higher-res lidar Researchers from Purdue University and École Polytechnique Fédérale de Lausanne (EPFL) devised a way to improve lidar and provide higher-resolution detection of nearby fast-moving objects through mechanical control and modulation of light on a silicon chip. "Frequency modulated continuous wave" (FMCW) lidar detects objects by scanning laser light from the top of a vehicl... » read more

Week In Review: Design, Low Power
By Jesse Allen - 11 Sep, 2020 - Comments: 0

Silvaco acquired the assets of Coupling Wave Solutions (CWS), including IP, patents, and analysis technologies. CWS provides tools for system-level interference analysis of complex SoCs that integrate analog, RF, and digital blocks. Silvaco said that the acquisition expands the company’s portfolio to address RF SOI (Silicon on Insulator) substrate analysis to accurately model and simulate noi... » read more

Blog Review: Sept. 9
By Jesse Allen - 09 Sep, 2020 - Comments: 0

Mentor's Jacob Wiltgen considers the recent advances in safety critical engineering and how automated the lifecycle can become, where tools form a set of checks and balances to ensure the accuracy of results. Cadence's Paul McLellan finds out what's new at TSMC, including a new R&D center, fab construction, capacity increases for existing nodes, and what the company sees for beyond its N... » read more

Power/Performance Bits: Sept. 9
By Jesse Allen - 09 Sep, 2020 - Comments: 0

Smaller, cheaper integrated photonics Researchers from the University of California Santa Barbara, California Institute of Technology (Caltech), and Ecole Polytechnique Fédérale de Lausanne (EPFL) developed a way to integrate an optical frequency comb on a silicon photonic chip. Optical frequency combs are collections of equally spaced frequencies of laser light (so called because when pl... » read more

Week In Review: Design, Low Power
By Jesse Allen - 04 Sep, 2020 - Comments: 0

Tools & IP Arm unveiled the Cortex-R82, a 64-bit, Linux-capable Cortex-R processor targeted for next-generation enterprise and computational storage solutions. The Cortex-R82 provides 2x performance depending on workload compared to previous Cortex-R generations and provides access of up to 1TB of DRAM for advanced data processing in storage applications. It offers an optional memory manag... » read more

Startup Funding: August 2020
By Jesse Allen - 02 Sep, 2020 - Comments: 0

Semiconductor startups were hot this month, with big funding going to designers and chip analytics. In automotive, one Chinese electric vehicle company raised another large round right before its IPO, and a LiDar maker's reverse merger gave it a cash infusion and set it on its own IPO road. Plus, a growing quantum computer developer saw a funding boost. This month, we feature 17 startups that c... » read more

Blog Review: Sept. 2
By Jesse Allen - 02 Sep, 2020 - Comments: 0

Arm's Pranay Prabhat highlights research into zero-power or low-power sensing devices and work toward designing a microcontroller that could fit with DARPA N-ZERO sensors. Mentor's Shivani Joshi provides a primer on the ODB++ standard data exchange file format that generates PCB design data files for use in fabrication, assembly, and test. Cadence's Paul McLellan shares some highlights fr... » read more

Power/Performance Bits: Sept. 1
By Jesse Allen - 01 Sep, 2020 - Comments: 0

Cooling sensors with lasers Researchers at the University of Washington developed a way to cool a solid semiconductor sensor component with an infrared laser. The laser was able to cool the solid semiconductor by at least 20 degrees C, or 36 F, below room temperature. The device uses a cantilever, similar to a diving board, that can oscillate in response to thermal energy at room temperatur... » read more

Week In Review: Design, Low Power
By Jesse Allen - 28 Aug, 2020 - Comments: 0

Tools & IP Monozukuri unveiled its IC/Package co-design tool, GENIO. GENIO integrates existing silicon and package EDA flows to create full co-design and I/O optimization of complex multi-chip designs.  It works seamlessly across all existing EDA flows and comprises floor planning, I/O planning and end-to-end interconnect planning combined with cross-hierarchical pathfinding optimization.... » read more

Blog Review: Aug. 26
By Jesse Allen - 26 Aug, 2020 - Comments: 0

Cadence's Paul McLellan shares some highlights from Hot Chips, including the massive growth in deep learning models, the basics of designing neural network models, and challenges involved in different approaches. Mentor's Colin Walls explores memory management units, its job of translating an address used by the CPU to an alternative address, and why this remapping is desirable and useful. ... » read more

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