Blog Review: Dec. 23

High performance and Arm; simulation, formal trends; security predictions; mask market optimism.


Cadence’s Paul McLellan checks out how Arm is becoming a powerhouse in the server and high-end space with the addition of new R&D and a focus on getting the most out of its architecture.

Siemens EDA’s Harry Foster continues his look at verification trends in FPGAs by checking out adoption of different simulation and formal technologies.

Synopsys’ Taylor Armerding looks ahead to 2021 with some predictions from exports on the state of software security, including the risks of social engineering and ransomware, cloud adoption, and low-code/no-code platforms.

Arm’s Ambroise Vincent introduces the Morello security architecture based on Capability Hardware Enhanced RISC Instructions (CHERI) and how to extend Memory Model Tools to include Morello and increase the coverage of the tools.

A Rambus writer explains how MACsec, a way to protect the security of data in motion between Ethernet-connected devices, works and what’s needed in a network security protocol.

In a video, VLSI Research’s Dan Hutcheson chats with Aki Fujimura of D2S about what the eBeam Initiative found in its 2020 Mask Maker’s Survey, including upbeat assessments of the market, EUV, and multi-beam mask writers.

Ansys’ Tyler Ferris explores several tops for how to build effective finite element analysis (FEA) models, including when to use different mesh generation types and finding a balance between accuracy and speed of processing.

SEMI’s Emir Demircan considers the use of fluorinated chemicals known as PFAS in semiconductor manufacturing and how to determine when use of a harmful chemical should be considered essential.

Lam Research’s Jami Haaning looks at the risk of forced and bonded labor in the semiconductor supply chain and what companies can do with suppliers to protect human rights.

Applied Materials’ Zhebo Chen explains selective processing, how it differs from traditional wafer processing methods, and how it can address scaling challenges at advanced nodes.

Silicon Labs’ Kevin Smith discusses how to calculate the phase noise and particular advantages of both cascaded (series) dual-loop PLL and the nested dual-loop PLL architectures.

Plus, check out the blogs featured in the latest Manufacturing, Packaging, & Materials newsletter:

In a conversation with Executive Editor Mark LaPedus, the SIA explains what the recent passage of an important U.S. government act means to the semiconductor industry.

SEMI’s Clark Tseng calculates that the total semiconductor equipment market — led by investments in China, Taiwan, and Korea — is on track to beat its previous high.

Amkor’s Ajay Sattu explains how keeping track of how a product moves through the supply chain provides real-time access to manufacturing information and meets end user safety requirements.

Quik-Pak’s Annette Teng recommends using backgrinding and die-attach film to optimize systems-in-package for consumer and communications devices.

Coventor’s Daebin Yim warns that for complex 3D memory devices, conventional DRC and metrology are no longer sufficient to achieve performance and yield goals.

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