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Jesse Allen

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Jesse Allen is the Knowledge Center administrator and a senior editor at Semiconductor Engineering.

Author's Latest Posts

Research Bits: Aug. 5
By Jesse Allen - 05 Aug, 2024 - Comments: 0

Measuring temperature with neutrons Researchers from Osaka University, National Institutes for Quantum Science and Technology, Hokkaido University, Japan Atomic Energy Agency, and Tokamak Energy developed a way to rapidly measure the temperature of electronic components inside a device using neutrons. The technique, called ‘neutron resonance absorption’ (NRA), examines neutrons being ab... » read more

Blog Review: July 31
By Jesse Allen - 31 Jul, 2024 - Comments: 0

Cadence's Jasmine Makhija explains how to boost the performance of CXL 3.0 by using NOP (No Operation) Insertion Hints in latency-optimized 256B Flit Mode, which enables the system to quickly revert to the low-latency path after temporarily switching to a higher-latency path due to error correction needs. Synopsys' Robert Fey finds that by automatically and dynamically linking requirements a... » read more

Research Bits: July 30
By Jesse Allen - 30 Jul, 2024 - Comments: 0

Embedded thermoelectric devices Researchers from the University of Pittsburgh and Carnegie Mellon University propose using locally embedded thermoelectric devices (TEDs) to perform active cooling inside circuits. “Circuits like clock generators and arithmetic and logic units (ALU) create high-frequency heat fluxes with their peak hot spots occurring on the microprocessor,” said Feng Xio... » read more

Research Bits: July 22
By Jesse Allen - 22 Jul, 2024 - Comments: 0

Sub-1nm gate Researchers from Korea's Institute for Basic Science, Sungkyunkwan University, Harvard University, and Korea Advanced Institute of Science and Technology (KAIST) found a method that enables epitaxial growth of 1D metallic materials with a width of less than 1 nm, which they used as a gate electrode of a miniaturized transistor. The team controlled the crystal structure of molyb... » read more

Blog Review: July 17
By Jesse Allen - 17 Jul, 2024 - Comments: 0

Cadence's Xin Mu explains the PCIe ECN Unordered IO (UIO) feature in the PCIe 6.1 specification, which defines a new wire semantic and related capabilities to enable multiple-path fabric support and helps avoid unnecessary traffic for better bandwidth and latency. Synopsys' Dana Neustadter, Gary Ruggles, and Richard Solomon highlight the latest updates in the CXL 3.1 standard, including new ... » read more

Research Bits: July 16
By Jesse Allen - 16 Jul, 2024 - Comments: 0

Kirigami-inspired mechanical computer Researchers from North Carolina State University developed a kirigami-inspired mechanical computer that uses a complex structure of rigid, interconnected polymer cubes to store, retrieve, and erase data without relying on electronic components. The system uses 1-centimeter plastic cubes, grouped into functional units consisting of 64 interconnected cubes. ... » read more

Startup Funding: Q2 2024
By Jesse Allen - 10 Jul, 2024 - Comments: 0

AI drew more investors to the chip industry in Q2. Four AI-focused chip startups receiving rounds of more than $100 million, targeting data center ASICs for transformers, highly flexible platforms for the embedded edge, dataflow processors, and mixed-signal neuromorphic chips. In-memory computing also helped boost AI, with three companies either incorporating it into their chips or providing sp... » read more

Blog Review: July 10
By Jesse Allen - 10 Jul, 2024 - Comments: 0

Cadence's Paul Graykowski suggests using real number modeling to streamline digital mixed-signal verification using logic simulators and hardware emulators. Siemens' John McMillan and Microsoft's Amit Kumar introduce the basics of 3D-IC, describe the flow and data management challenges, look at the evolution of TSMC 3DBlox 1.0 and 2.0, and detail a physical verification and reliability analy... » read more

Blog Review: June 26
By Jesse Allen - 26 Jun, 2024 - Comments: 0

Cadence's Neelabh Singh examines the Gen4 link recovery mechanism in USB4 Version 2.0, an autonomous process that is initiated by a router when it encounters uncorrectable error events, and identified verification challenges. Synopsys' Gary Ruggles and Priyank Shukla highlight improvements to PCIe 7.0 that will enable secure data transfers and boost bandwidth for the next generation of AI an... » read more

Blog Review: June 19
By Jesse Allen - 19 Jun, 2024 - Comments: 0

Siemens' John McMillan and Todd Burkholder suggest using an automatic formal-based approach to verifying chiplet package connections early in the design process. Cadence's Veena Parthan explores the intricacies of wind tunnel testing in automotive design and how the collaborative relationship between computational fluid dynamics (CFD) and wind tunnels has resulted in accelerated and more nua... » read more

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