Author's Latest Posts


Blog Review: Oct. 8


Siemens' Azat Latypov presents a stochastic-aware optical proximity correction strategy that demonstrated an order-of-magnitude reduction in the probability of stochastic defects for both SRAM and logic designs, sacrificing minor edge placement error in return for much lower failure rates. Cadence's Dimitry Pavlovsky introduces the AMBA CHI Chip-to-Chip (C2C) protocol, which extends the CHI ... » read more

Research Bits: Oct. 7


Doping oxide insulator improves SiGe conductivity Researchers from TU Wien, Johannes Kepler University Linz, and TU Bergakademie Freiberg manufactured a silicon-germanium (SiGe) transistor using an alternative approach that involves doping the insulating oxide layer to produce a long-range effect that extends into the semiconductor. Called modulation acceptor doping (MAD), the technique ena... » read more

Chip Industry Startup Funding: Q3 2025


The third quarter of 2025 was dominated by massive rounds for companies developing AI chips and quantum computers. Over $2.5 billion went to AI, with wafer-scale chip maker Cerebras leading the pack with a $1.1 billion raise. While several edge AI companies received backing, the quarter saw a marked shift towards solutions for the data center as firms seek to reduce the cost and power consumpti... » read more

Blog Review: Oct. 1


Synopsys' Chun-Soo Kim and Hoseong Kim suggest making the entire design flow local layout effect-aware to identify and address issues early and ultimately improve PPA by avoiding overly pessimistic designs. Siemens' Kirk Fabbri explores the power distribution network, focusing on power plane capacitance and how it varies with the dynamic switching characteristics of the load and dielectric c... » read more

Research Bits: Sept. 30


Hybrid memory for edge training and inference Researchers from CEA-Leti, Université Grenoble Alpes, CEA-List, the French National Centre for Scientific Research (CNRS), the University of Bordeaux, Bordeaux INP, IMS France, Université Paris-Saclay, and the Center for Nanosciences and Nanotechnologies developed a hybrid memory system that combines the traits of ferroelectric capacitors (FeCAP)... » read more

Blog Review: Sept. 24


Siemens' Harry Foster warns of a big drop in first-time silicon success as more system companies tackle developing their own chip without the accumulated knowledge around flows, sign-off criteria, and coverage closure in a landscape where even small oversights in methodology can lead to multimillion-dollar respins. Synopsys' Godwin Maben warns that skyrocketing power consumption is a critica... » read more

Research Bits: Sept. 23


Opto-electrical excitation of MTJs Researchers at the University of Greifswald, International Iberian Nanotechnology Laboratory, Max Planck Institute for the Science of Light, and Aarhus University advanced the use of magnetic tunnel junctions (MTJs) for neuromorphic computing. The team developed a hybrid opto-electrical excitation scheme that combines electrical currents with short laser p... » read more

Blog Review: Sept. 17


Siemens' John McMillan explores the fundamentals of IC package thermal resistance, modeling strategies, and why die-level thermal analysis in 3D-ICs is increasingly essential for ensuring device reliability. Cadence's Jasmine Makhija provides an overview of the TEE Device Interface Security Protocol (TDISP), which helps safeguard PCIe devices within Trusted Execution Environments by providin... » read more

Research Bits: Sept. 16


Beyond-EUV resists Researchers from Johns Hopkins University, East China University of Science and Technology, École Polytechnique Fédérale de Lausanne (EPFL), Soochow University, Brookhaven National Laboratory, and Lawrence Berkeley National Laboratory propose a combination of new resist materials and a higher-powered EUV process that could enable smaller chip feature sizes. The "beyond... » read more

Blog Review: Sept. 10


Cadence's Satish Kumar C explains Port-Based Routing, a feature in in CXL 3.0 and 3.1 that changes how CXL switches operate within a CXL fabric to enable the creation of much larger, more flexible, and more efficient topologies. Siemens' Bill Hargin demystifies copper foil thickness and weight measurements and why being precise has an impact on signal integrity and crosstalk simulations.... » read more

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