Falling first-time silicon success; prioritize energy efficiency early; chiplet power tradeoffs; verifying double-precision division; security deadline.
Siemens’ Harry Foster warns of a big drop in first-time silicon success as more system companies tackle developing their own chip without the accumulated knowledge around flows, sign-off criteria, and coverage closure in a landscape where even small oversights in methodology can lead to multimillion-dollar respins.
Synopsys’ Godwin Maben warns that skyrocketing power consumption is a critical challenge for AI systems and finds that prioritizing energy efficiency during the earliest architectural phases can yield 30% to 50% power savings, while only single-digit improvements are achievable during implementation or signoff.
Cadence’s Naomi Mitchell considers the challenges involved in balancing power tradeoffs for chiplets and how to go from managing early-stage power models to ensuring power integrity across interconnected dies.
Arm’s Simon Tatham uses formal verification to ensure proper operation of the double-precision division function as part of an effort to create a set of optimized assembly-language routines for basic floating-point arithmetic for use with CPUs without hardware floating point.
Keysight’s Zahra Khani warns that there is only a year to comply with the EU’s Cyber Resilience Act, which mandates that even legacy products report actively exploited vulnerabilities within 24 hours, and urges makers of IoT devices, networking gear, and embedded systems to create a software bill of materials.
Ansys’ Robert Etter considers some of the challenges involved in designing the next generation of aircraft that are powered by electricity, have vertical takeoff and landing capabilities, and can navigate situations in which aircraft separation can be measured in feet rather than miles.
SEMI’s James Amano invites members of the semiconductor manufacturing supply chain to participate in creating a standardized methodology for reporting the use and presence of regulated substances, starting with PFAS.
Plus, check out the blogs featured in the latest Manufacturing, Packaging & Materials newsletter:
Amkor’s Mahenthren Palaniappan explores how the optimization of solder paste vision detection settings is crucial for reducing clip lifting defects.
Lam Research’s Taeyeon Oh explains how hybrid metallization presents an alternative to conventional copper dual damascene and reduces total via/line resistance by about 55%.
Synopsys’ Greg Sorber highlights how quantum computing could reshape our understanding of the world.
Microtronic’s Errol Akomer offers ways to look at more wafer surface without dramatically impacting budgets and production schedules.
yieldWerx’s Aftkhar Aslam details the benefits of integrating a wide range of data from disparate sources into a unified analytical environment.
Electronic System Design Alliance’s Bob Smith converses with PDF Solutions’ John Kibarian about the role automated AI agents play in handling the vast amounts of data created by multiple stakeholders.
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