Blog Review: Oct. 8

Siemens’ Azat Latypov presents a stochastic-aware optical proximity correction strategy that demonstrated an order-of-magnitude reduction in the probability of stochastic defects for both SRAM and logic designs, sacrificing minor edge placement error in return for much lower failure rates.

Cadence’s Dimitry Pavlovsky introduces the AMBA CHI Chip-to-Chip (C2C) protocol, which extends the CHI specification and supports topologies that enable a number of functionally similar chiplets to perform coherent processing as well as the connection of an I/O coherent or fully coherent device to the system host.

Synopsys’ Andrew Appleby, Daryl Seitzer, and Mohammad Tanveer share how they customized foundation IP to meet the low-voltage operation requirements of an optical networking chip for edge AI.

Arm’s Wathsala Vithanage and Ola Liljedahl delve into relaxed memory models and the pitfalls that can arise from assuming that acquire/release fences provide stronger guarantees of correct ordering than they do, leading to unsafe orderings.

Keysight’s Carrie Browen finds that the software-defined vehicle transformation is leading to a new generation of global R&D collaboration and automation platforms that support continuous development and validation across distributed teams and systems.

Ansys’ Caty Fairclough checks out the advanced air mobility landscape, including electric vertical takeoff and landing (eVTOL) vehicles, and how simulation tools can help address optimization and safety validation challenges.

SEMI’s Scarlett Bickerton finds that proposed U.S. patent fee changes are not only about rates, but also about how fees are structured, applied across different types of filers, and administered in practice.

And for a change of pace from reading, watch a recent video:

The Rise Of AI Co-Processors and why keeping AI hardware current and relevant is becoming a challenge.

Coherent vs. non-coherent interfaces, heterogeneous vs. homogeneous, and other Benefits And Challenges Of Using Chiplets.

How in-device monitoring can improve the reliability and lifespan of semiconductors through Silicon Lifecycle Management.

Where Virtual Metrology In Semiconductor Manufacturing works best and why.

The potential of Virtual Twins is enormous, but building them is far from simple.

The Evolution of DRAM and how and why this tried-and-true memory is changing.

Using AI For Fault Detection And Classification In Manufacturing, supervised vs. unsupervised FDC, and the impact on yield.

The Challenges In Stacking HBM and what changes are needed to stack 24 layers of high-bandwidth memory.

Preparing For The Quantum Computing Age by designing chips and systems to withstand brute-force attacks by quantum computers.

Unique designs and multi-die assemblies are forcing innovations at the leading edge of testing, like Advanced Part Average Testing For Chips.

Machine Learning In Semiconductor Manufacturing and how advances and limitations are defined by the data.

The promise, reality, and evolution of artificial intelligence in semiconductor manufacturing introduced in AI, From A To Z.

Workload-Specific Hardware Accelerators and what differentiates accelerators from other processing elements.

New DRAM standard aims to solve a critical bottleneck, in What’s Different About HBM4.

Issues In Ramping Advanced Packaging and why traditional daisy chain approaches fall short.