Unique designs and multi-die assemblies are forcing innovations at the leading edge of testing.
Part average testing, one of the mainstays of semiconductor test, is becoming much more challenging at advanced nodes and in multi-die assemblies. In the past, PAT produced a Gaussian distribution that made it relatively simple to find outliers. That’s no longer the case. Advanced packaging and leading-edge designs have unique attributes that determine which rules apply, such as the thickness of the wafer or unique zonal issues. Aftkhar Aslam, co-founder and CEO of yieldWerx, talks about what causes low yield in these chips, why multi-modal approaches are needed to ensure good yield, and why neighboring dies can make the testing process significantly more complicated.
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